Pioneer DVL-90 Service Manual page 100

DVL-90, DVL-700
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[78 |__| — [Powersupply fordgial creuit_ConmedctiowsV.— SSCS
[79 [@ND | = |Groundiordigtalcieut —SCSCSCSCSCSCSCSCSSCSCSCSSC*Y
ps0 [Sas |
pee [Sat
pes [sao | |
[84 [SOUTH | O [Serial output whichis used the DMA channel of OPU_Outputsthe uppernbble———SSCS~CS
fs |SA07__|
1/0 |Connect the data bus of the main CPU
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[2s [VOD | — [Power supply for digital creut_ConnedcttoweV.SSCSC~"~*S*~*~"~'"'~*~*~*~S~S~*S
[80 [end [= |Groundfordigtalcieut —SSCSCSCSCSCSCSCSCSCSCSCSSCSCSCSCSCS*Y
[ot |sabs__|
[82 [Sade _| |
V/O |Connect the data bus of the main CPU
[es [san1__|
| 95 |DUTY50 | O | Always outputs the duty 50% pulse Apply the reference voltage of each PWM signal of demodulation system. |
XIRQ1O |
Low for require the interrupt against to the main CPU Setable the output pins with the register. |
[a8 |TSTSTS_| 1 [Setthe [Sito operate the tat node TostmodeforHighimp® SSCS
[28 [BMODES | |
F700 [BMODET |
F107 [BMODED |
F102 [BMODES |
[708 JBUNRI _|_1_[Separaon test conte pin ofthe ilemal RAM _Tnpuis Lwin he achaluse SSCS
[roa |VOD__| — [Power supply for dal creat Comedetio8V SSCS
Ground for digital circuit
| 106 [GND
AXTLO | 0 | 36.864MHz or 24.576MHz crystal connect pin which is oscillated the reference clock to use the audio output circuit.
XTL When input a signal from the extemal, connect to AXTLI.
VOD
110 |CKCD
1
Connect the address bus of the main CPU
Set to perform the any test in the test mode
Power supply for digital circuit Connedct to +5V.
Reference clock of CD audio output Inputs 16.9MHz.
Ground for digital circuit
When the master clock is AV synchronized, outputs the pulse which is frequency divided the audio side clock
_
ie (AXTLI input) for apply to the PLL circuit,
When the master clock is AV synchronized, outputs the pulse which is frequency divided the video side clock
(DMACKI input) for apply to the PLL circuit.
Frequency divided signal which is connected to AXTL pin and use for DAC control
Frequency is changed by the mode.
Bit clock output to DAC and audio decoder It is 48fs or 64fs of the source.
LRCK signal output to DAC and audio decoder
Outputs the compression data when source is AC3/MPEG and outputs CHO/CH1 when source is linear.
1 113 |PREF
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116 |LRCK
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DIFOUTO
DIFOUT1
VALID
Output CH2/CH3 when source is linear
Busy signa! for output control the serial output of SOUTL, SOUTH pins
Digital output by switching the compression data and linear data
When linear data is output, output the same as that of the DIFOUT1.
Digital out for linear data only Outputs CHO&CH1/AC3/MPEG/CD of DVD linear correspond to the sourca.
When source is AC3/MPEG, it becomes High level during effective data output :
Inputs linear data after the decode from audio decoder This data is digital output. Audio datais slave movement. |
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100