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5 Hardware Design Files
5.1 Schematic
Figure 5-1
through
Figure 5-2
illustrate the schematics.
D1
40V
Input
D2
25V 6A
TP3
J3
BAT+
1
7P
40V
7P
7P
6P
2
6P
6P
3
5P
5P
5P
4P
4
4P
4P
5
3P
3P
3P
2P
6
2P
2P
1P
7
1P
1P
8
BAT-
BAT-
TP9
R6
10.0
C5
R7
220nF
10.0
R8
10.0
C7
R9
220nF
10.0
R11
10.0
C9
R12
220nF
10.0
R13
10.0
R14
10.0
C12
220nF
NT1
VSS
BAT-
Net-Tie
VSS
TP24
BAT-
TP26
TP27
GND
GND
VSS
VSS
TP28
TP29
GND
GND
VSS
VSS
SLUUCY9 – NOVEMBER 2023
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TP1
R1
REGSRC
U1
0
BAT
R2
17
15
BAT
REGOUT
16
100
REGSRC
C3
C4
VC7
18
VC5
100pF
1uF
VC6
CHG
19
10
VC4A
CHG
TP5
TP6
VC5
20
9
DSG
VC4B
DSG
VC4
1
VC3A
VSS
VSS
VC3
2
12
VC3B
SCL
VC2
3
13
VC2
SDA
VC1
4
14
VC1
ALERT
VC0
5
VC0
TS
8
TS
TP10
6
21
SRP
EP
VC7
7
11
SRN
VSS
TP12
BQ76905RGR
VC6
VSS
C6
TP13
0
VC5
TP14
VC4
C8
TP16
0
VC3
TP17
VC2
C10
TP18
220nF
VC1
TP19
VC0
C13
DSG
220nF
TP20
TP21
TP22
SRP
SRN
C15
R15
C16
C17
0.1uF
100pF
0.1uF
5.1k
C19
GND
VSS
VSS
0.1uF
TP33
R17
R18
100
100
R19
10M
5,6,
R21
7,8
1,2,3
0.001
C20
C21
Q1
0.1uF
0.1uF
Figure 5-1. Schematic Diagram Monitor
Copyright © 2023 Texas Instruments Incorporated
TP2
REGOUT
REGOUT
J1
R3
REGSRC
C1
10k
C2
1
1uF
2
TP4
1µF
TP7
50V
VSS
REGOUT
J5
R4
10k
1
2
TP8
REGOUT
J7
R5
10k
1
2
TP11
Pull-ups to
REGOUT
25V 6A Max
CHG
BAT+
7P
PACK+
TP23
C14
PACK+
0.1uF
PACK-
R16
5.1k
C18
PACK-
0.1uF
Output
J9
TP34
E3
D5
R20
D6
10M
16V
5,6,
7,8
1,2,3
TP25
PACK-
Q2
Hardware Design Files
External I2C
J2
Connection
1
uC_SCL
2
J4
4
3
R41
100
2
J6
1
1
uC_SDA
2
U2
U3
VSS
E1
E2
R42
100
On-board (EV2400)
MCU connections
VSS
REGOUT
WAKE
TP15
D3
R10
TS
3
1
1
4
2
3
1.0k
Q3
S1
D4
2
Thermistor and Wake
1.8V
1
button for TS pin
J8
RT1
VSS
C11
470pF
50V
VSS
BQ76905 Evaluation Module
SDA
SCL
GND
1P
17
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