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When the frequency is controlled by the PLL, the fre-
quency convergence time increases as the frequency differ-
ence increases when the set frequency is changed. To sup-
plement this, the ASIC is used before control by the PLL IC
to bring the VCO oscillation frequency close to the desired
frequency. As a result, the VCO CV voltage does not change
and is always stable at approximately 2.5V.
The desired frequency is set for the PLL IC by the ASIC
(IC610) through the 3-line "SDO1", "PCK_RF", "/PCS_RF"
serial bus. Whether the PLL IC is locked or not is monitored
by the ASIC through the "PLD" signal line. If the VCO is not
the desired frequency (unlocked), the "PLD" logic is low.
The modulation signal of the Low-speed data is applied to
pin 23 of the PLL IC (IC403).
X401
16.8MHz
IC403
TCXO
SDO1
PCK_RF
/PCS_RF
PLLMOD
6. Control Circuit
The control circuit consists of the ASIC (IC610) and its pe-
ripheral circuits. IC610 mainly performs the following:
1) Switching between transmission and reception by PTT
signal input.
2) Reading system, zone, frequency, and program data from
the memory circuit.
3) Sending frequency program data to the PLL.
4) Controlling squelch on/off by the DC voltage from the
squelch circuit.
5) Controlling the audio mute circuit by decode data input.
6-1. ASIC
The ASIC (IC610) is a 32-bit RISC processor, equipped
with peripheral function and ADC/DAC.
This ASIC operates at 18.432MHz clock and 3.3V/1.5V
DC. It controls the fl ash memory, SRAM, DSP, the receive
circuit, the transmitter circuit, the control circuit, and the dis-
play circuit and transfers data to or from an external device.
CIRCUIT DESCRIPTION
Q401,Q402
D402~D405
D407,D409~D411
Loop
Filter
PLL
IC404 (1/2)
CV
VCO MOD
IC402
ASSIST
100C
Fig. 6 PLL block diagram
The modulation signal is digital data of a sampling fre-
quency of 96kHz set for the PLL IC by the DSP (IC603)
through the "PLLMOD" line.
5-4. Local switch (D412, D413)
The connection destination of the signal output from the
buffer amplifier (Q408) is changed with the diode switch
(D413) that is controlled by the transmission power supply,
50T, and the diode switch (D412) that is controlled by the
receive power supply, 50R. If the 50T logic is high, it is con-
nected to a send-side pre-drive (Q102). If the 50T logic is
low, it is connected to a receive-side mixer (Q201).
D415
Q405
Q408
BUFF
BUFF
VCO
AMP
AMP
50CS
Doubler
BPF
6-2. Memory circuit
The memory circuit consists of the ASIC (IC610), the
SRAM (IC605), and the flash memory (IC601). The flash
memory has a capacity of 32M-bit that contains the trans-
ceiver control program for the ASIC and stores the data. It
also stores the data for transceiver channels and operating
parameters that are written by the FPU. This program can
be easily written from external devices. The SRAM has a
capacity of 1M-bit that contains work area and data area.
■ Flash memory
Note: The fl ash memory stores the data that is written by
the FPU (KPG-141D), tuning data (Deviation, Squelch, etc.),
and firmware program (User mode, Test mode, Tuning
mode, etc.).
■ SRAM (Static memory)
Note: The SRAM has a temporary data area and work area.
NX-220
D412,D413
T/R
to TX stage
SW
15
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