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Setting
PCI Express GEN2 Device Register Settings
Completion Timeout
ARI Forwarding
Atomicop Requester Eanble
Atomicop Egress Blocking
IDO Request Enable
IDO Completion Enable
LTR Mechanism Enable
End-End TLP Prefix Blocking
PCI Express GEN2 Link Register Settings
Target Link Speed
Clock Power Management
Compliance SOS
Hardware Autonomous Width
Description
In device Functions that support Completion Timeout programmability,
software to modify the Completion Timeout value. 'Default' 50us to. 50ms. If 'Shorter' is
selected, software will use shorter timeout ranges supported by hardware. If 'Longer' is
selected, software will use longer timeout ranges.
If supported by hardware and set to 'Enabled', the Downstream Port disables its
traditional Device Number filed being 0 enforcement when turning a Type1
Configuration. Request into a Type0 Configuration Request, permitting access to
Extended Functions in an ARI Device immediately below the Port.
Default value: 'Enabled'.
If supported by hardware and set to 'Enabled', this function initiates AtomicOp Requests
only if Bus Master Enable bit is in theCommand Register Set.
Default value: 'Disabled'.
If supported by hardware and set to 'Enable', outbound AtomicOp Requests via Egress
Ports will be blocked.
Default value: 'Disabled'.
If supported by hardware and set to 'Enable', this permits setting the number of ID-Based
Ordering (IDO) bit (Attribute[2]) requests to be initiated.
Default value: 'Disabled'.
If supported by hardware and set to 'Enable', this permits setting the number of ID-Based
Ordering (IDO) bit (Attribute[2]) requests to be initiated.
Default value: 'Disabled'.
If supported by hardware and set to 'Enable', this enables the Latency Tolerance
Reporting (LTR) Mechanism.
Default value: 'Disabled'.
If supported by hardware and set to 'Enable', this function will block forwarding of TLPs
containing End-End TLP Prefixes.
Default value: 'Disabled'.
If supported by hardware and set to 'Force to X.X GT/s' for Downstream Ports, this sets
an upper limit on Link operational speed by restricting the values advertised by the
Upstream component in itstraining sequences.
When 'Auto' is selected HW initialized data will be used.
The options are: Auto, 'Force to 2.5 GT/s', 'Force to 5.0 GT/s', 'Force to 8.0 GT/s', and
'Force to 16.0 GT's'.
If supported by hardware and set to 'Enable', the device is permitted to use CLKREQ#
signal for power management of Link clock in accordance to protocol.
Default value: 'Disabled'.
If supported by hardware and set to 'Enable', this will force LTSSM to send SKP Ordered
Sets between sequences when sending Compliance Pattern or Modified Compliance
Pattern.
Default value: 'Disabled'.
If supported by hardware and set to 'Disabled', this will disable the hardware's ability to
change link width except width size reduction for the purpose of correcting unstable link
operation. The default setting is 'Enabled'.
allows system
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