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Appendix B
Timing Diagrams
Figure B-2. Input Timing and the Analog Input Timing Engine
_i
Selected Reference Trigger
Terminal
_i
Terminal
_i
Terminal
_i
Terminal
_i
Terminal
Time
From
*
t
PFI
1
RTSI
STAR
*
The delay ranges given for PFI and RTSI represent the fastest and slowest terminal routing within the
trigger group for a given condition (maximum or minimum timing). This difference can be useful when
two external signals will be used together and the relative timing between the signals is important.
B-4 | ni.com
Selected Start Trigger
Selected Pause Trigger
Sample Clock Timebase
Sync Sample Clock Timebase
Convert Clock Timebase
Sync Convert Clock Timebase
Selected Sample Clock
Figure B-3. Input Timing Diagram
Terminal
t
1
_i
Table B-1. Input Timing
To
PFI_i
RTSI_i
STAR_i
Reference Trigger
Start Trigger
Pause Trigger
SI Start
SI
Counter
Block
SI_TC
SI2
SI2_TC
Counter
Block
Start
t
1
Min (ns)
4.2
6.4
0.9
2.2
0.9
—
Terminal
Terminal
RTSI
Terminal
p_AI_Convert
1
Terminal
Max (ns)
15.2
19.2
2.0
3.0
—
2.8
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