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Circuit Descriptions, Abbreviation List, and IC Data Sheets
9.7
IC Data Sheets
This section shows the internal block diagrams and pin
configurations of ICs that are drawn as "black boxes" in the
electrical diagrams (with the exception of "memory" and "logic"
ICs).
9.7.1
Diagram B1A, NCP5422ADR2G (IC 7U00)
Block Diagram
V
R
CC
OSC
BIAS
V
CC
8.6 V
−
7.8 V
IS+1
+
IS−1
−
−
70 mV
IS+2
+
IS−2
−
−
FAULT
70 mV
S
Q
Set
Dominant
−
R
+
0.25 V
−
E/A OFF
5.0 A
E/A1
1.0 V
V
COMP1
FB1
Pin Configuration
1
GATE(H)1
GATE(L)1
GND
BST
IS+1
IS−1
V
FB1
COMP1
A
= Assembly Location
WL
= Wafer Lot
Y
= Year
WW = Work Week
Figure 9-4 Internal block diagram and pin configuration
CURRENT
SOURCE
RAMP1
GEN
CLK1
OSC
CLK2
S
non−overlap
Reset
Dominant
FAULT
PWM
Comparator 1
R
FAULT
RAMP1
0.425 V
−
S
+
non−overlap
Reset
FAULT
Dominant
PWM
Comparator 2
R
FAULT
RAMP2
E/A OFF
0.425 V
FAULT
1.2 mA
−
−
+
E/A2
1.0 V
V
COMP2
FB2
SO−16
16
GATE(H)2
GATE(L)2
V
CC
R
OSC
IS+2
IS−2
V
FB2
COMP2
EBJ1.0U
9.
RAMP2
BST
BST
GATE(H)1
V
CC
GATE(L)1
BST
GATE(H)2
V
CC
GATE(L)2
GND
F_15400_129.eps
240505
EN 147
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