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Circuit Descriptions, Abbreviation List, and IC Data Sheets
9.1.1
Large Signal Panel (LSP)
The LSP consists of two power supply blocks and one
deflection block. These two power supply blocks are the Main
Supply and the Standby Supply. The Main Supply delivers
power for the CRT deflection circuit, audio amplifiers and the
convergence output stage. The Standby Supply delivers power
for the SSB and the GDE/ACS processor. The deflection
blocks deliver three stable anode high voltages,and the
horizontal/vertical deflection for the three CRTs.
9.1.2
Medium Signal Board (MSB)
The MSB performs the following functions:
•
GDE controller that controls the convergence and CRT
output processor (HOP). Beside that, it communicates with
the EBJ module (=SSB) to perform the necessary CRT
alignment.
•
CRT output processor that delivers the CRT deflection
signal source for large signal to drive the CRT's deflection.
•
Convergence processor and Convergence driving
amplifier that ensure the three CRT beam landing is
converged on the desired location.
•
Interface circuit to complete the links between EBJ module
and desired circuit.
•
Power management circuit to process large signal supply
for EBJ module and the other circuit.
9.1.3
Small Signal Board (SSB)
The Eco Baby Jag (=EBJ) module is the same digital module
developed by Philips for LCD and PDP with a difference
(components fitted differently) in video interface for CRT RPTV
(video interface: RGBHV (1366X1080i@60Hz) and
communication port is UART).
The module contains:
•
ATSC/QAM/NTSC tuner and demodulator.
•
AV decoder (NTSC). Picture enhancement like 3D comb
filter, LTI/CTI, noise reduction, film mode, EDDI.
•
Rear AV interface:
–
AV1: YPbPr /CVBS, L, R (6 cinches block).
–
AV2: YPbPr/CVBS, L, R (6 cinches block).
–
HDMI/DVI share L, R with AV1.
–
AV3: SVHS/CVBS, L, R.
–
SPDIF audio output for analogue and digital.
•
System controller and standby processor.
•
Audio decoder/processor.
•
2X10W class D audio amplifier.
There are interfaces on the SSB for the following panels:
•
Audio constant monitor output: L, R (additional panel
derived from EBJ).
•
Side AV interface: SVHS /CVBS, L, R and USB1.1.
•
Front control.
•
Keyboard.
Description below refers to the block diagrams in chapter 6
"Block Diagrams, Test Point Overview, and Waveforms".
Analog Reception
The TV receives multimedia information by tuning the Hybrid
tuner (for analog and digital reception) to one of many 6 MHz
input channels available via a cable connection. When the
input channel is an analog channel, the signal is processed via
the NTSC decoder and the VBI data decoder of the MPIF.
Digital Reception
The TV receives multimedia information by tuning to one of
many 6 MHz input channels available via a cable connection.
When the input channel is a digital channel, it is processed via
the QAM demodulator and then passed to the multi-media
EBJ1.0U
processor (VIPER), which handles the synchronization and
display of audio-visual material.
Signal Processing
The AVIP together with the MPIF device is used to perform the
input decoding of a single stream of analog audio and video
broadcast signals. In addition, the AVIP is used for decoding
and presentation of audio output streams. The main data
connection between MPIF and AVIP is done via an I
The AVIP converts the incoming video data to ITU-656 format
for communication to the VIPER IC.
The audio data is transferred between the AVIP and VIPER
2
using I
S.
The AVIP IC is controlled by the VIPER via the I
The key part in the system, the VIPER, performs almost all key
features, like video quality enhancement, motion
compensation, picture-in-picture processing, and others. It is a
completely digital IC with a TriMedia DSP (Digital Signal
Processor) core and a MIPS microcontroller core. The DSP
and some additional cores are used to do the video feature
processing and some auxiliary sound feature processing. The
MIPS microcontroller core is used for all internal and external
controlling tasks including a system wide I
The VIPER provides a primary digital (YUV or RGB) output to
the LVDS transmitter.
Note: For a more detailed SSB circuit description, please refer
to the BL2.xU Service Manual (3122 785 15570). The here
described chassis is an ECO version of the BL2.x-chassis, e.g.
it does not have the POD interface. However, the AVIP, MPIF,
PNX, and VIPER part are comparable.
9.2
General Overview
9.3
Large Signal Panel (LSP)
9.3.1
Horizontal Output Circuit and EW Correction Circuit
Note: Description below refers to diagram E3 (middle section).
Horizontal drive pulse (33.75 kHz, 45% duty cycle) from the
HOP circuit on the MSB is fed to 7807 on the LSP.
Transistor 7807 is switched "on" and "off" and drives the
Horizontal Output Transistor 7801 through the base driver
transformer 5808 which is operating in flyback mode: when
7807 is "on", the current energy is stored in 5808 and released
to drive 7801 when 7807 is "off". Base driver is supplied by
130VS through 3839/3840/2836
7801 drives the horizontal output stage. Horizontal output
stage is supplied by 130VS through 5801 to the output stage.
This 130VS charges up Scap 2816 together with Yokes and
being switched by 7801.
During the scanning period, 7801/6810 is "on", which means
the voltage of 2816/2850 is applied on the Yokes and so a
sawtooth current is flowing through the Yokes and completes
the scanning. The horizontal yokes of Red, Green and Blue
tube are connected in parallel.
During the flyback period, the tuning capacitor 2818 and the
yokes consist as a resonant circuit and resonates at the
frequency of 1/5.5us while 7801/6810 is "off".
Transformer 5801 produces a plus and minus 13-volt supply for
the Vertical Output circuit.
Voltage from Pin 7 of 5801 is rectified by 6802 to produce the
+200 volt supply for the CRTs.
Voltage from Pin 5 is rectified by 6801 to produce the Filament
voltage. This voltage is filtered by 2804 to provide
9.
EN 141
2
D bus.
2
C bus.
2
C bus.
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