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tWRPRE
This item Holds DDR timing parameter tWRPRE. WR to PRE same bank minimum delay in tCK
cycles. Supported Range is 18-159.
Options: Auto (Default)
tXP
This item Holds DDR timing parameter txP. Power up to any command minmum delay in tCK
cycles Supported Range is 4-16.
Options: Auto (Default)
tXPDLL
This item Holds DDR timing parameter txP. Power up to RD / WR minmum delay in tCK cycles.
Applicable for DDR4 in case of exit from PPD when DRAM is configured to slow-exit mode.
Supported Range is 4-63.
Options: Auto (Default)
tPRPDEN
This item Holds DDR timing parameter tPRPDEN. PRE to power down minmum delay in tCK
cycles. Suported Range is 1-3.
Options: Auto (Default)
tRDPDEN
This item Holds DDR timing parameter tPRPDEN. RD to power down minmum delay in tCK
cycles. Supported Range is 4-95.
Options: Auto (Default)
tWRPDEN
This item Holds DDR timing parameter tPRPDEN. WR to power down minmum delay in tCK
cycles. Supported Range is 4-159.
Options: Auto (Default)
tCPDED
This item Holds DDR timing parameter tCPDED. Power down to command bus tri-state delay in
tCK cycles (for DDR4) supported Range is 1-7 in 1N mode.
Options: Auto (Default)
tAONPD
This item Holds DDR timing parameter tAONPD. Supported range is 4-30.
Options: Auto (Default)
tREFIx9
This item maximum time allowed between refreshes to a rank (in intervals of 1024 DCLK cycles).
Should be programmed to 8* tREFI/ 1024 (to allow for possible delays from ZQ or ISOC)
Options: Auto (Default)
tXSDLL
This item delay between DDR SR exit and the first command that requires data RD / WR from
DDR.
Options: Auto (Default)
tZQOPER
This item defines the period required for ZQCL after SR exit.
Options: Auto (Default)
tMOD
The time between MRS command and any other command in DCLK cycles.
Options: Auto (Default)
38 | 6. Tweaker Menu
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