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MAIN(OP DRV) SCHEMATIC DIAGRAM
5
4
OPEN
C4923
1
2
3
L4902
10u
M_REG4.9
To MAIN IF
M_REG4.9
NQL38DK-100X
C4902
10
GND
L4904
10u
OPEN
R4959
0Ω
C4935
(1005)
L4903
10u
To MAIN IF
M_REG4.9
NQL38DK-100X
C4932
10
GND
ST305R4NV
VDIRS
To DSP
CLK27O
VD_FZ
OPDRV_CLK
OPDRV_CS
To CPU
OPDRV_OUT
OPDRV_IN
OPDRV_PS
OPDRV_RST
H_OFFSET
To DSP
H_GAIN
NOTES: 1. For the destination of each signal and further line connections that are cut off from this diagram, refer to "BOARD INTERCONNECTIONS".
2. The parts with marked ( ) is not used.
IC4903
S-1112B29MC-W
5
4
OPEN
C4924
OPEN
IC4902
1
2
3
OPEN
C4927
OPEN
C4925
M_REG4.9V
C4903
10
REG_3.1V_IC4901
10
Q4901
A1
1
NC
B10
27
NT
F10
23
GNDD
C4905
0.1
H9
52
DVDD
H10
21
RSTB
D9
56
SCK
B1
TL4902
2
PLS3
B2
TL4937
37
PLS4
J10
TL4920
20
MONI0
A9
29
TEST
E10
24
CS
D10
25
SIN
G10
22
OSCIN
G9
53
VD_IS
R4953
E9
55
SOUT
470
B9
58
PDWNB
F9
54
VD_FZ
C9
TL4901
57
Ach
PLS1
A8
TL4943
30
PLS2
C10
26
MODESEL
C4940
OPEN
CN106
OP Type
NonMega
K241
(No.YF259<Rev.001>)2-15
OPEN
C4941
C4947
0.1
C4942
R4955
0.1
R4954
10k
10k
R4906
560k
R4907
1M
C4908 R4904
C4909
10k
R4905
0.01
0.1
33k
R4903
8.2k
C4907
C4911
CH
0.1
100p
A5
33
OP3INP
C2
38
PHTRIN
A2 36
TEST2
J9
51
MONI1
D1
4
IRISOUTA
A7 31
GNDA
C1
3
AVDD3
K9
18
NC
K2
11
NC
F2
41
OP1INP
IC4901
AN41904A-X
G1
7
OP1INN
E1
5
OP1OUT
E2 40
OP0OUT
D2
39
GND5A
F1
6
AVDD5
H1
8
OP0INN
Bch
Cch
Dch
G2
42
OP0INP
K10
19
NC
C4933
OPEN
OPEN
C4934
2-16(No.YF259<Rev.001>)
MAIN(OP DRV)
0
1
C4915
0.001
CH
TL4938
R4911
R4924
100
12k
TL4951
C4912
0.1
R4961
100k
R4962
100k
C4943
0.1
R4987
120
C4913
0.1
C4914
0.0022
C4916
0.1
R4988
R4950 R4949
120
150k
10k
C4921
0.022
yf259_y10762001a_rev0.1
Z_PTR_AD
Z_PTR_AD
F_PTR_AD
To CPU
F_PTR_AD
OP_THRMO
OP_THRMO
To OP BLOCK(K241)
CN106
QGF0543F3-25X
1
Z_LED
2
Z_VCC
3
FOCUS01
4
FOCUS04
5
FOCUS03
6
FOCUS02
7
8
DUMP-
9
HGOUT-
10
HGVSS-
11
DRIVE-
12
DRIVE+
13
HGOUT+
14
HGVCC+
15
DUMP+
16
17
18
19
F_LED
20
F_VCC
21
ZOOM01
22
ZOOM04
23
ZOOM03
24
ZOOM02
25
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