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Schematic
4
Schematic
Figure 6
to
Figure 9
provide the schematics for this EVM.
J1 and J8
0 V to 50 V
0A to 5A
TP2
J1
INPUT_DCY
INPUT_DCY
J3
0 V to 100 V
0A to 5A
J3
J4
1
1
C2
DNP
2
100uF
DNP
TP5
J8
GND_DCY
GND_DCY
GND_DCY
16
MLTLDO2EVM-037 Evaluation Module
INPUT_DCY
C3
DNP
DNP
C6
C7
C8
47µF
100nF
1uF
1uF
ADJ_DCY
OUTPUT_DCY
INPUT_DCY
Figure 6. Generic DCY Package Schematic
Copyright © 2020, Texas Instruments Incorporated
D1
DNP
100V
U1
3
2
IN
OUT
TP3
DNP
4
1
ADJ_DCY
TAB
ADJ
R1
0
R2
DNP
10.0k
C1
DNP
TP4
100nF
D2
DNP
100V
J7
2
DNP
C12
R3
1
100nF
10.0k
J10
1
2
OUTPUT_DCY
3
4
DNP
5
6
TP1
OUTPUT_DCY
1
C4
C5
C9
C10
DNP
C11
DNP
DNP
47µF
100µF
DNP
100nF
10uF
1uF
TP6
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J2 and J9
0 V to 50 V
0A to 5A
J2
OUTPUT_DCY
J6
0 V to 100 V
0A to 5A
J5
J6
1
2
J9
GND_DCY
SBVU065 – May 2020
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