Harman Kardon AVR 370 Service Manual page 174

6
1.8V Power Supply
+1.8V_SCALER ADV8003_DVDD_1.8V
L1401
HCB1608KF-600T30
ADV8003_DVDD_DDR_1.8V
ADV8003_PVDD_DDR_1.8V
L1402 L1410
HCB1608KF-600T30 HCB1608KF-600T30
D
ADV8003_CVDD_1.8V
L1403
HCB1608KF-600T30
CUP12457Z
ADV8003_AVDD3_1.8V_1
L1404
HCB1608KF-600T30
ADV8003_AVDD3_1.8V_2
L1420
HCB1608KF-600T30
ADV8003_AVDD3_1.8V_3
L1421
HCB1608KF-600T30
ADV8003_PVDD1_1.8V
L1405
HCB1608KF-600T30
ADV8003_PVDD2_1.8V
L1406
HCB1608KF-600T30
C
ADV8003_PVDD3_1.8V
L1407
HCB1608KF-600T30
ADV8003_PVDD5_1.8V
L1408
HCB1608KF-600T30
+5VH1
ADV8003_PVDD6_1.8V
HD_TX_CK+
L1409 HD_TX_CK-
HCB1608KF-600T30
HD_TX_DATA0+
HD_TX_DATA0-
HD_TX_DATA1+
HD_TX_DATA1-
HD_TX_DATA2+
HD_TX_DATA2-
R1414
RN1408
R1415
HDMI_DSP_SCLK
HDMI_DSP_MCLK
HDMI_DSP_LRCK
HDMI_DSP_SDATA3
R1416
33X4
RN1409 1005 / 1/16W / 0ohm
HDMI_DSP_SDATA2
HDMI_DSP_SDATA1
HDMI_DSP_SDATA0
HDMI_DSP_SPDIF
33X4
R1417
ARC_SPDIF2
R1418
ARC_SPDIF1
B
ADV8003_DVDD_IO_3.3V ADV8003_DVDD_IO_3.3V
C1498
C1499
R1423
HDMI_SDA R1424
HDMI_SCL 1005 / 1/16W / 0ohm
1005 / 1/16W / 0ohm
R1425
33ohm
ADV8003_INT2 R1426
33ohm
ADV8003_INT1
R1427 33ohm
ADV8003_INT0
1005 / 1/16W / 0ohm
ADV8003_SPI_SCK 1005 / 1/16W / 0ohm
ADV8003_SPI_MOSI
R1430 R1428 39ohm
ADV8003_SPI_MISO 1005 / 1/16W / 0ohm
R1429
ADV8003_SPI_CS
R1431
A
R1442
ADV8003_RST
1005 / 1/16W / 0ohm
5
3.3V Power Supply
ADV8003_DVDD_IO_3.3V
ADV8003_AVDD1_3.3V
L1411 L1412
HCB1608KF-600T30 HCB1608KF-600T30
+3.3V_ADV8003
A1
OSD[23]/D[7]
4.7K R1507 B2
OSD[22]/D[6]
4.7K R1508 B1
OSD[21]/D[5]
4.7K R1509 C2
OSD[20]/D[4]
4.7K R1510 C1
OSD[19]/D[3]
4.7K R1511 D3
OSD[18]/D[2]
4.7K R1512 D2
OSD[17]/D[1]
4.7K R1513 D1
OSD[16]/D[0]
E3
4.7K R1514
OSD[15]/CS
4.7K R1515 E2
OSD[14]/MOSI
4.7K R1516 E1
OSD[13]/SCK
4.7K R1517 F4
OSD_IN[12]
4.7K R1518 F3
OSD_IN[11]
4.7K R1519 F2
OSD_IN[10]
4.7K R1520 F1
OSD_IN[9]
4.7K R1521 G4
OSD_IN[8]
4.7K R1522 G3
OSD_IN[7]
4.7K R1523 G2
OSD_IN[6]
4.7K R1524 G1
OSD_IN[5]
4.7K R1525 H4
OSD_IN[4]
4.7K R1526 H3
OSD_IN[3]
4.7K R1527 H2
H1 OSD_IN[2]
4.7K R1528
OSD_IN[1]
4.7K R1529 J4
OSD_IN[0]
4.7K R1530 B3
OSD_VS
4.7K R1531 J3
OSD_HS
4.7K R1532 A2
OSD_DE
4.7K R1533 A3
OSD_CLK/E_CLK
4.7K R1534
L4
P[35]
L3
L2 P[34]
P[33]
L1
P[32]
M4
P[31]
M3
P[30]
M2
P[29]
M1
P[28]
N4
P[27]
N3
P[26]
N2
P[25]
N1
P[24]
P4
P[23]
P3
P[22]
P2
P[21]
P1
R4 P[20]
P[19]
R3
P[18]
R2
P[17]
R1
P[16]
T2
P[15]
T1
P[14]
U4
P[13]
U3
P[12]
U2
P[11]
U1
P[10]
V4
P[9]
V3
P[8]
V2
P[7]
V1
W4 P[6]
P[5] IC1401
W3
P[4]
W2
P[3]
W1
P[2]
Y2
P[1]
Y1
P[0]
K1
R1535 VS CVIADV8003KBCZ8B_A
B6
SFL
J2
HS
1005 / 1/16W / 0ohm K2
PCLK
J1
DE
B17
RX_CP
A17
RX_CN
B18
RX_0P
A18
RX_0N
B19
RX_1P
A19
RX_1N
B20
RX_2P
A20
RX_2N
D16
RX_5V
C16
RX_HPD
1K(1%) D19
RTERM
1K(1%)
C6
SCLK
D6
MCLK
C5
DSD_CLK
A6
AUD_IN[5]
C4
AUD_IN[4]
B5
A5 AUD_IN[3]
A4 AUD_IN[2]
AUD_IN[1]
B4
AUD_IN[0]
56ohm A7
ARC2_OUT
56ohm B7
ARC1_OUT
C15
NC_001
D15
NC_002
C14
NC_003
D14
NC_004 ADV8003-->All port to NC
A15
NC_005
B15
NC_006
A14
NC_007
B14
NC_008
R1434
10P
1005 / 1/16W / 0ohm
10P
+3.3V_ADV8003
ADV8003_DVDD_IO_3.3V
16 15 14
R1441
CVTRT1N441C
1Kohm
Q1401
1 2 3
NC
R1445 33
4 3
DDR2 Memory layout Guidelines:
ADV8003_AVDD2_3.3V
L1413
HCB1608KF-600T30
1. DDR2 Modules and ADV8003 to be placed as close together as possible.
2. Balanced T-routing if possible for all shared connections between ADV8003 and DDR2 Memories
3. All traces to be inpedance matced.
4. All traces to be routed on the aame layer(s) -outer layer(s) if possible
5. CK & CK , DDR_DQS3 and DDR_DQS3 , DDR_DQS2 and DDR_DQS2 , DDR_DQS1 and DDR_DQS1 , DDR_DQS0 and DDR_DQS0 ,
to be treated as a differential pair : - Routed adjacently and in parallel on the same layer.
6. Match CK trace length to CK trace lenght to 20mils (0.5mm)
7. There are 4 x Byte-wide data lines on the DDR2 interface
- DDR_DM3, DDR_DQS3, DDR_DQS3 , DDR_DQ31-DDR_DQ24
- DDR_DM2, DDR_DQS2, DDR_DQS2 , DDR_DQ23-DDR_DQ16
- DDR_DM1, DDR_DQS1, DDR_DQS1 , DDR_DQ15-DDR_DQ8
- DDR_DM0, DDR_DQS0, DDR_DQS0 , DDR_DQ7-DDR_DQ0
Data lines within a byte should be matched to 50mil (1.27mm)
- Precise lenght matching of these traces is ctitical.
8. Isolate data and address/control tracks to each other by at least 20mil (0.5mm)
9. Place 47ohm series termination resistors as dose to source (AVD8003) as possible on the following signals
- Address signals (DDR_A12-DDR_A0 aod DDR_BA2-DDR_BA0)
- Clock Differential Signals (CK, CK ), -(Use discrete resistors for these tow signals)
- Control (CKE) and Command ( CS , RAS , CAS , WE ) Signals
- Data Mask Signals (DDR_DM3-DDR_DM0)
10. Place 47ohm series termination resistors in middle of the trace on the following signals
- Data Bus Signals (DDR_DQ31-DDR_DQ0)
- Data Strobe Signals (DDR_DQS3/ DDR_DQS3 -DDR_DQS0/ DDR_DQS0 )
11. Keep sutbs shorts on CK, CK lines
12. Do not share a DQS signal resistor pack with a non-data-group signal
13. Route VREF as far away from other signals as possible
AC16
DDR_VREF ADV8002_DDR_VREF
AA15 SD_CK
DDR_CK
Y15 SD_CKB
DDR_CKB
AB15 SD_CKE
DDR_CKE
AA13 SD_CSB
DDR_ CS
AB14
DDR_ RAS SD_RASB
Y13
SD_CASB
DDR_ CAS
AC15 SD_WEB
DDR_ WE
AB13 SD_BA0
DDR_BA[0]
AC13 SD_BA1
DDR_BA[1]
AC14 SD_BA2
DDR_BA[2]
AB12 SD_A0
DDR_A[0]
AC11 SD_A1
DDR_A[1]
AA11 SD_A2
DDR_A[2]
AB11
DDR_A[3] SD_A3
Y11
SD_A4
DDR_A[4] AC9
SD_A5
DDR_A[5]
AB10 SD_A6
DDR_A[6]
AC10 SD_A7
DDR_A[7]
AA9 SD_A8
DDR_A[8]
AC8 SD_A9
DDR_A[9]
AC12 SD_A10
DDR_A[10]
Y9 SD_A11
DDR_A[11]
AB9 SD_A12
DDR_A[12]
AB6 SD_DM3
DDR_DM[3]
Y7 SD_DQS3
DDR_DQS[3]
AA7
SD_DQSB3
DDR_ DQS[3] AB7
SD_DQ31
DDR_DQ[31]
AB5 SD_DQ30
DDR_DQ[30]
AB8 SD_DQ29
DDR_DQ[29]
AC5 SD_DQ28
DDR_DQ[28]
AC6 SD_DQ27
DDR_DQ[27]
AA5 SD_DQ26
DDR_DQ[26]
AC4 SD_DQ25
DDR_DQ[25]
AC7 SD_DQ24
DDR_DQ[24]
AB4 SD_DM2
DDR_DM[2]
Y3 SD_DQS2
DDR_DQS[2]
AA4 SD_DQSB2
DDR_ DQS[2]
Y5
SD_DQ23
DDR_DQ[23] AC3
SD_DQ22
DDR_DQ[22]
AB1 SD_DQ21
DDR_DQ[21]
AC2 SD_DQ20
DDR_DQ[20]
AB2 SD_DQ19
DDR_DQ[19]
AA1 SD_DQ18
DDR_DQ[18]
AB3 SD_DQ17
DDR_DQ[17]
AC1 SD_DQ16
DDR_DQ[16]
AA19 SD_DM1
DDR_DM[1]
AB17 SD_DQS1
DDR_DQS[1]
AC18 SD_DQSB1
DDR_ DQS[1]
AC19
DDR_DQ[15] SD_DQ15
Y19
SD_DQ14
DDR_DQ[14] AB19
SD_DQ13
DDR_DQ[13]
AB16 SD_DQ12
DDR_DQ[12]
AA17 SD_DQ11
DDR_DQ[11]
AC17 SD_DQ10
DDR_DQ[10]
Y17 SD_DQ9
DDR_DQ[9]
AB18 SD_DQ8
DDR_DQ[8]
AA20 SD_DM0
DDR_DM[0]
AB22 SD_DQS0
DDR_DQS[0]
AC22 SD_DQSB0
DDR_DQSB[0]
AC20 SD_DQ7
DDR_DQ[7]
Y21
SD_DQ6
DDR_DQ[6] AB21
SD_DQ5
DDR_DQ[5]
AB23 SD_DQ4
DDR_DQ[4]
AA23 SD_DQ3
DDR_DQ[3]
AC21 SD_DQ2
DDR_DQ[2]
AC23 SD_DQ1
DDR_DQ[1]
AB20 SD_DQ0
DDR_DQ[0]
L20
HPD_TX1 HDMI_TX_HPD1
L22
TX1_C+
L23
TX1_C-
H22
TX1_2+ H23
TX1_2-
J22
TX1_1+
J23
TX1_1-
K22
TX1_0+
K23
TX1_0-
T20 HDMI_TX_HPD2
HPD_TX2
U22
TX2_C+
U23
TX2_C-
P22
TX2_2+
P23
TX2_2-
R22
TX2_1+
R23
TX2_1- T22
TX2_0+
T23
TX2_0-
M22
HEAC_1+
M23
HEAC_1-
V22
HEAC_2+
V23
HEAC_2-
K20
DDC1_SCL
J20
DDC1_SDA
P20
DDC2_SCL R20
DDC2_SDA
Plese component as close as possible to
F23
CEC1 ADV8002_CEC1 R_XT1 & R_TX2 on the ADV8003
N20
CEC2
M20 R1478
R_TX1
U20 R1477
R_TX2
B22
COMP1 E22 Keep this away from any high speed signals
COMP2
G20
ELPF1
G21
ELPF2
A22
RSET1
F20
RSET2
A23
VREF
D22
DAC1
D23
DAC2
E23
DAC3
B23
DAC4
C22
DAC5
C23
DAC6
128Mbit Serial Flash
CN15
CJP07GA193ZY
10022H-07C
HDMI_CEC_SEL
R1447
SCK
1005 / 1/16W / 0ohm
GND
13 12 11 10 9 R1448
MOSI OPEN
1005 / 1/16W / 0ohm
VCC
R1449
CS
R1452 0_NC
R1450 ADV8002_CEC1
1005 / 1/16W / 0ohm
MISO R1453 0
CEC
4 5 6 7 8 1005 / 1/16W / 0ohm R1454 0
GND MCU_CEC
R1455
CEC_SEL
4.7K
+3.3V_ADV8003
AVR170/270_Used
2
DDR_A0
DDR_A1
DDR_A2
DDR_A3
DDR_A4
DDR_A5
DDR_A6
DDR_A7
DDR_A8
DDR_A9
DDR_A10
DDR_A11
DDR_A12
ADV8002_SDRAM_LINE DDR_BA0
DDR_BA1
DDR_DM1
RN1416 DDR_DM0
SD_DQ27 DDR_DQ27
47X4 DDR_RASB
SD_DQ30
DDR_DQ30 DDR_CASB
SD_DQ25
DDR_DQ25
DDR_WEB
SD_DQ28
DDR_DQ28 DDR_CSB
RN1417
SD_DQ21
Place resistor across CK and CK differential DDR_DQ21
DDR_CKE
lines just before the "T" split SD_DQ16 47X4 DDR_CK
DDR_DQ16
DDR_CKB
SD_DQ23 DDR_DQ23
SD_DQ29
DDR_DQ29
R1498
RN1418
SD_DQ26
DDR_DQ26
100_NC
47X4
SD_DQSB2
DDR_DQSB2
SD_DQS2
DDR_DQS2
SD_CK R1497 47
DDR_CK
SD_DQ18
SD_CKB R1496 47 DDR_DQ18
DDR_CKB
R1495 47 RN1419
SD_A11
DDR_A11
SD_DQ22 DDR_DQ22
RN1410
47X4
SD_CKE SD_DQ17
DDR_CKE DDR_DQ17
47X4
SD_WEB SD_DQ20
DDR_WEB DDR_DQ20
SD_BA2 SD_DQ19
DDR_BA2 DDR_DQ19
SD_BA0 RN1420
DDR_BA0
SD_DQ8
DDR_DQ8
RN1411
SD_A0 SD_DQ15 47X4
DDR_A0 DDR_DQ15
47X4
SD_CASB SD_DQSB1 DDR_DQSB1
DDR_CASB
SD_CSB SD_DQS1 DDR_DQS1
DDR_CSB
SD_RASB RN1421
DDR_RASB
SD_DQ11
DDR_DQ11
RN1412
47X4
SD_BA1 SD_DQ14
DDR_BA1 DDR_DQ14
47X4
SD_A10 SD_DQ9
DDR_A10 DDR_DQ9
SD_A1 SD_DQ12
DDR_A1 DDR_DQ12
RN1422
SD_A3
DDR_A3
SD_DQ5 DDR_DQ5
RN1413
47X4
SD_A8 SD_DQ0
DDR_A8 DDR_DQ0
47X4
SD_A6 SD_DQ7
DDR_A6 DDR_DQ7
SD_A4 SD_DQ13
DDR_A4 DDR_DQ13
SD_A2 RN1423
DDR_A2
SD_DQ10
DDR_DQ10
RN1414
SD_A7 SD_DQSB0 47X4
DDR_A7 DDR_DQSB0
47X4
SD_A5 SD_DQS0 DDR_DQS0
DDR_A5
SD_A12 SD_DQ2 DDR_DQ2
DDR_A12
SD_A9 RN1424
DDR_A9
SD_DQ6
DDR_DQ6
RN1415
47X4
SD_DQ24 SD_DQ1
DDR_DQ24 DDR_DQ1
47X4
SD_DQ31 SD_DQ4
DDR_DQ31 DDR_DQ4
SD_DQSB3 SD_DQ3
DDR_DQSB3 DDR_DQ3
SD_DQS3
DDR_DQS3
SD_DM0 R1494 47 DDR_DM0
SD_DM1 R1493 47 DDR_DM1
SD_DM2 R1492 47
DDR_DM2
ADV8002_SDRAM_LINE SD_DM3 R1491 47
DDR_DM3
C1517 1uF
HDMI_HEAC1+
C1516 1uF R1490 0
HDMI_TX_HPD1
C1515 1uF
HDMI_HEAC2+
C1514 1uF R1489 0
HDMI_TX_HPD2
HDMI_DDC_SCL1
HDMI_DDC_SDA1
HDMI_DDC_SCL2
HDMI_DDC_SDA2
C1513 OPEN
470(%)
470(%)
C1512 OPEN +5VH1 AVR370 ONLY
ADV8003_PVDD3_1.8V
C1509 0.012
ADV8003_AVDD2_3.3V R1475 2.7K(1%)
R1474 180(1%) C1508 0.15
C1507 0.012
R1473 2.7K(1%)
R1472 180(1%) C1506 0.15
Place as close as possible and in the
same side of the PCB as ADV8003
AVR2700 USE
R1457
AVR2700 NC
L1423, C1519, R1506, JK1402
R1455, R1456, Q1402, D1401, RY1401
R1459, L1424,C1503
C1515, C1514, R1487, R1488, R1484
R1481, R1482, R1418
PMP
AVR2700 -> USED
AVR3700 -> NC
Q1402
RY1401 R1458
HDMI_CEC1
0
ISSUE
ANAM
R1459
HDMI_CEC2 MULTI. LAB
0
12.08.02
L1424
ST+5V
HCB1608KF-600T30
BC1-5S-R
D1401
2012.04.16
KDS160
1
- Route VREF at least 2cm away form other signals to minmize coupling
- Design traces as short and wide as possible between the voltage source and VREF
- Place capacito as dose as possible to VREF pin
Plade the termination resistor at the Plade the termination resistor at the
end of the differential trace end of the differential trace
DDR_CK DDR_CK
DDR_CKB DDR_CKB
ADV8002_DDR_VREF ADV8002_DDR_VREF
C1555 0.1 J2 G8 C1556 0.1 J2 G8
VREF IC1303 DQ0 DDR_DQ0 VREF IC1304 DQ0
G2 G2
DQ1 DDR_DQ1 DQ1
H7 H7
DQ2 DDR_DQ2 DQ2
M8 H3 M8 H3
A0 DQ3 DDR_DQ3 DDR_A0 A0 DQ3
M3 H1 M3 H1
A1 DQ4 DDR_DQ4 DDR_A1 A1 DQ4
M7 H9 M7 H9
A2 DQ5 DDR_DQ5 DDR_A2 A2 DQ5
N2 F1 N2 F1
A3 DQ6 A3 DQ6
N8 F9 DDR_DQ6 DDR_A3 N8 F9
A4 DQ7 A4 DQ7
N3 C8 DDR_DQ7 DDR_A4 N3 C8
A5 DQ8 A5 DQ8
N7 C2 DDR_DQ8 DDR_A5 N7 C2
A6 DQ9 A6 DQ9
P2 D7 DDR_DQ9 DDR_A6 P2 D7
P8 A7 DQ10 D3 DDR_DQ10 DDR_A7 P8 A7 DQ10 D3
P3 A8 DQ11 D1 DDR_DQ11 DDR_A8 P3 A8 DQ11 D1
A9 DQ12 DDR_DQ12 DDR_A9 A9 DQ12
M2 D9 M2 D9
A10 DQ13 DDR_DQ13 DDR_A10 A10 DQ13
P7 B1 P7 B1
A11 DQ14 DDR_DQ14 DDR_A11 A11 DQ14
R2 B9 R2 B9
A12 DQ15 DDR_DQ15 DDR_A12 A12 DQ15
L2 L2
BA0 DDR_BA0 BA0
L3 B7 L3 B7
BA1 UDQS BA1 UDQS
F7 DDR_DQS1 DDR_BA1 F7
LDQS LDQS
DDR_DQS0
B3 B3
UDM UDM
F3 A8 DDR_DM3 F3 A8
LDM UDQS LDM UDQS
E8 DDR_DQSB1 DDR_DM2 E8
LDQS DDR_DQSB0 LDQS
K7 K7
RAS DDR_RASB RAS
L7 K9 L7 K9
CAS ODT DDR_CASB CAS ODT
K3 K3
WE DDR_WEB WE
L8 A2 L8 A2
CS NC_01 DDR_CSB CS NC_01
E2 E2
NC_02 NC_02
L1 L1
BA2 BA2
K2 R3 DDR_BA2 K2 R3
CKE NC_04 CKE NC_04
J8 R8 DDR_CKE J8 R8
CK NC_05 CK NC_05
K8 R7 DDR_CK K8 R7
CK NC_06 CK NC_06
DDR_CKB
+1.8V_DDR
+1.8V_DDR
A1 A3 A1 A3
VDD_01 VSS_01 VDD_01 VSS_01
E1 E3 E1 E3
VDD_02 VSS_02 VDD_02 VSS_02
J9 J3 J9 J3
VDD_03 VSS_03 VDD_03 VSS_03
M9 N1 M9 N1
VDD_04 VSS_04 VDD_04 VSS_04
R1 P9 R1 P9
VDD_05 VSS_05 VDD_05 VSS_05
A9 A7 A9 A7
VDDQ_01 VSSQ_01 VDDQ_01 VSSQ_01
C1 B2 C1 B2
VDDQ_02 VSSQ_02 VDDQ_02 VSSQ_02
C3 B8 C3 B8
VDDQ_03 VSSQ_03 VDDQ_03 VSSQ_03
C7 D2 C7 D2
VDDQ_04 VSSQ_04 VDDQ_04 VSSQ_04
C9 D8 C9 D8
VDDQ_05 VSSQ_05 VDDQ_05 VSSQ_05
E9 E7 E9 E7
G1 VDDQ_06 VSSQ_06 F2 G1 VDDQ_06 VSSQ_06 F2
G3 VDDQ_07 VSSQ_07 F8 G3 VDDQ_07 VSSQ_07 F8
VDDQ_08 VSSQ_08 VDDQ_08 VSSQ_08
G7 H2 G7 H2
VDDQ_09 VSSQ_09 VDDQ_09 VSSQ_09
G9 H8 G9 H8
VDDQ_10 VSSQ_10 VDDQ_10 VSSQ_10
J1 J7 J1 J7
VDDL VSSDL VDDL VSSDL
+1.8V_DDR
ADV8003 DDR POWER
DDR2 VREF Generation
- Shared between DDR2 Interface and DDR2 Memorise
+1.8V_DDR
ADV8002_DDR_VREF
D2+
D2 SHIELD
D2-
D1+
D2 SHIELD
2012.08.02
D1-
D0+
D1 SHIELD
D0-
CK+
D1 SHIELD
CK-
HDMI_CEC1 CE REMOTE
HDMI_HEAC1+ HEAC+
HDMI_DDC_SCL1 DDC CLK
HDMI_DDC_SDA1 DDC DATA
+5VH1
GND
L1422
+5V
HDMI_TX_HPD1
HCB1608KF-600T30
HP DET&HEAC-
D2+
D2 SHIELD
D2-
D1+
D2 SHIELD
2012.08.02
D1-
D0+
D1 SHIELD
D0-
CK+
D1 SHIELD
CK-
HDMI_CEC2 CE REMOTE
HDMI_HEAC2+ HEAC+
HDMI_DDC_SCL2 DDC CLK
+5VH1
HDMI_DDC_SDA2 DDC DATA
GND
L1423
+5V
HCB1608KF-600T30
HP DET&HEAC-
HDMI_TX_HPD2
OPEN
AVR370 ONLY
REVISION 2 4 6
1 3 5 7
SCHEMATIC DIAGRAM
AVR270/370
MODEL
DESIGN CHECK APPROVE DRAWING NO
CUPxxxxxZ
S.K.S L.J.H W.Y.Y
(Scaler & Tx)
12.08.02 11.12.27 11.12.27
D
DDR_DQ16
DDR_DQ17
DDR_DQ18
DDR_DQ19
DDR_DQ20
DDR_DQ21
DDR_DQ22
DDR_DQ23
DDR_DQ24
DDR_DQ25
DDR_DQ26
DDR_DQ27
DDR_DQ28
DDR_DQ29
DDR_DQ30
DDR_DQ31
DDR_DQS3
DDR_DQS2
DDR_DQSB3
DDR_DQSB2
DDR_BA2
C
B
A
SHEET
4
9