Page 1 Document Part Number: 361834-001 August 2004 This document provides information on the design, architecture, function, and capabilities of the HP Compaq dc7100 and dx6100 Series Business Desktop Computers. This information may be used by engineers, technicians, administrators, or anyone needing detailed information on...
Page 2 Adobe, Acrobat, and Acrobat Reader are trademarks or registered trademarks of Adobe Systems Incorporated. The only warranties for HP products and services are set forth in the express warranty statements accompanying such products and services. Nothing herein should be construed as constituting an additional warranty. HP shall not be liable for technical or editorial errors or omissions contained herein.
Page 3: Table Of Contents
Contents 1 Introduction 1.1 About this Guide ............. 1–1 1.1.1 Online Viewing .
Page 4 Contents 3 Processor/Memory Subsystem 3.1 Introduction ..............3–1 3.2 Pentium 4 Processor .
Page 5 Contents 5.6.1 Keyboard Interface Operation ..........5–18 5.6.2 Pointing Device Interface Operating .
Page 6 Contents 8.3 Boot Functions............. . . 8–3 8.3.1 Boot Device Order .
Page 7: Introduction
Introduction About this Guide This guide provides technical information about HP Compaq dx7100 and dc6100 series personal computers that feature the Intel Pentium 4 processor and the Intel 915G chipset. This document describes in detail the system's design and operation for programmers, engineers, technicians, and system administrators, as well as end-users wanting detailed information.
Page 8: Model Numbering Convention
Introduction Model Numbering Convention The model numbering convention or HP systems is as follows: 361834-001 Technical Reference Guide...
Page 9: Serial Number
Serial Number The unit's serial number is located on a sticker placed on the exterior cabinet. The serial number is also written into firmware and may be read with HP Diagnostics or Insight Manager utilities. Notational Conventions The notational guidelines used in this guide are described in the following subsections.
Page 10: Common Acronyms And Abbreviations
Introduction Common Acronyms and Abbreviations Table 1-1 lists the acronyms and abbreviations used in this guide. Table 1-1 Acronyms and Abbreviations Acronym or Abbreviation Description ampere alternating current ACPI Advanced Configuration and Power Interface analog-to-digital Analog-to-digital converter ADD or ADD2 Advanced digital display (card) Accelerated graphics port application programming interface...
Page 11 Introduction Table 1-1 Acronyms and Abbreviations Acronym or Abbreviation Description Channel, chapter centimeter cache/memory controller CMOS complimentary metal-oxide semiconductor (configuration memory) Cntlr controller Cntrl control codec 1. coder/decoder 2. compressor/decompressor Compaq central processing unit CRIMM Continuity (blank) RIMM cathode ray tube 1.
Page 12 Introduction Table 1-1 Acronyms and Abbreviations Acronym or Abbreviation Description ESCD Extended System Configuration Data (format) Environmental Variable (data) ExCA Exchangeable Card Architecture FIFO first in/first out flag (register) frequency modulation fast page mode (RAM type) Floating point unit (numeric or math coprocessor) Frames per second Foot/feet gigabyte...
Page 13 Introduction Table 1-1 Acronyms and Abbreviations Acronym or Abbreviation Description Kb/KB kilobits/kilobytes (x 1024 bits/x 1024 bytes) Kb/s kilobits per second kilogram kilohertz kilovolt pound local area network liquid crystal display light-emitting diode Low pin count large scale integration LSb/LSB least significant bit/least significant byte logical unit (SCSI) Meter...
Page 14 Introduction Table 1-1 Acronyms and Abbreviations Acronym or Abbreviation Description Personal computer Printed circuit assembly peripheral component interconnect PCI-E PCI Express pulse code modulation PCMCIA Personal Computer Memory Card International Association PCI express graphics Power factor correction personal identification number Programmed I/O Part number POST...
Page 15 Introduction Table 1-1 Acronyms and Abbreviations Acronym or Abbreviation Description SIMD Single instruction multiple data SIMM single in-line memory module SMART Self Monitor Analysis Report Technology system management interrupt system management mode SMRAM system management RAM serial presence detect SPDIF Sony/Philips Digital Interface (IEC-958 specification) Spare part number standard parallel port...
Page 16 Introduction Table 1-1 Acronyms and Abbreviations Acronym or Abbreviation Description Volts direct current VESA Video Electronic Standards Association video graphics adapter VLSI very large scale integration VRAM Video RAM watt Wake-On-LAN WRAM Windows RAM zero flag zero insertion force (socket) 1-10 361834-001 Technical Reference Guide...
Page 17: System Overview
System Overview Introduction The HP Compaq dc7100 and dx6100 Series Business Desktop Computers (Figure 2-1) deliver an outstanding combination of manageability, serviceability, and compatibility for enterprise environments. Based on the Intel Pentium 4 processor with the Intel 915G Chipset, these systems emphasize performance along with industry compatibility.
Page 18: Features And Options
System Overview Features And Options This section describes the standard features. 2.2.1 Standard Features The following standard features are included on all series: Intel Pentium 4 processor in LGA775 (Socket T) package Integrated graphics controller PC2700 and PC3200 support, with PC3200 DIMMs supplied, IDE controller providing serial and parallel ATA support Hard drive fault prediction Eight USB 2.0 ports...
Page 19 System Overview Table 2-1 shows the differences in features between the different PC series based on form factor: Table 2-1 Difference Matrix by Form Factor USDT Series dc7100 dc7100 dx6100 dx6100 dc7100 System Board Type custom custom custom µATX µATX Serial and parallel ports Optional [1] Standard...
Page 20: Mechanical Design
System Overview 2.3 Mechanical Design This guide covers six form factors: Ultra Slim Desktop (USDT)—Very slim design that can be used in a tradition desktop (horizontal) orientation or as a small tower mounted in the supplied tower stand. Small Form Factor (SFF)—A small-footprint desktop requiring minimal desk space. Slim Tower (ST)—Slim design that can be used in a tradition desktop (horizontal) orientation or as a small tower mounted in the supplied tower stand.
Page 21: Cabinet Layouts
MultiBay device bay USB ports 7, 8 MultiBay device eject lever Power LED Microphone audio In jack MultiBay device / HD activity LED Headphone audio Out jack Power button Figure 2-2. HP Compaq dc7100 USDT Front View Technical Reference Guide 361834-001...
Page 22 Headphone audio Out jack CD-ROM drive acitvity LED USB ports 7, 8 Diskette drive eject button Hard drive activity LED CD-ROM media tray Power LED CD-ROM drive open/close button Power button Figure 2-3. HP Compaq dc7100 SFF Front View 361834-001 Technical Reference Guide...
Page 23 Diskette media door USB ports 7, 8 CD-ROM drive acitvity LED hard drive activity LED Diskette drive eject button Power LED CD-ROM media tray Power button CD-ROM drive open/close button Figure 2-4. HP Compaq dx6100 ST Front View Technical Reference Guide 361834-001...
Page 24 Diskette drive media door Power LED Diskette drive activity LED Hard drive activity LED Diskette drive eject button Headphone audio Out jack USB ports 7, 8 Microphone audio In jack Figure 2-5. HP Compaq dx6100 MT Front View 361834-001 Technical Reference Guide...
Page 25 Diskette drive media door Power LED Diskette drive activity LED USB ports 7, 8 Diskette drive eject button Headphone audio Out jack Hard drive activity LED Microphone audio In jack Figure 2-6. HP Compaq dc7100 CMT Front View Technical Reference Guide 361834-001...
Page 26 VGA monitor connector (DB-15) Keyboard connector (PS/2) AC input connector Line audio In USB ports 1, 2 Headphone / Speaker audio Out USB ports 3 - 6 Figure 2-7. HP Compaq dc7100 USDT, Rear View 2-10 361834-001 Technical Reference Guide...
Page 27 Mouse connector (PS/2) Parallel port (DB-25) Keyboard connector (PS/2) Serial port (DB-9) Line audio In AC input connector Headphone / Speaker audio Out USB ports 1, 2 Figure 2-8. HP Compaq dc7100 SFF, Rear Views Technical Reference Guide 361834-001 2-11...
Page 28 USB ports 3 - 6 Mouse connector (PS/2) NIC (LAN) connector (RJ-45) VGA monitor connector (DB-15) Serial port (DB-9) USB ports 1, 2 Headphone / Speaker audio Out Figure 2-9. HP Compaq dc7100 ST, Rear Views 2-12 361834-001 Technical Reference Guide...
Page 29 Line audio In jack Microphone In jack NIC (LAN) connector (RJ-45) USB ports 5, 6 NOTE: [1] Switch not present on SKUs that feature auto-ranging power supply. Figure 2-10. HP Compaq dx6100 MT, Rear View Technical Reference Guide 361834-001 2-13...
Page 30 VGA monitor connector (DB-15) USB ports 1-4 Serial port connector (DB-9) Line audio Out jack Keyboard connector (PS/2)) Line audio In jack AC line connector NIC (LAN) connector (RJ-45) Figure 2-11. HP Compaq dc7100 CMT, Rear View 2-14 361834-001 Technical Reference Guide...
Page 31: Chassis Layouts
UIltra Slim Desktop Chassis The Ultra Slim Desktop (USDT) chassis used for the HP Compaq dc7100 models uses a compact, space-saving form factor. Item...
Page 32 Small Form Factor / Slim Tower Chassis The chassis layouts for the Small Form Factor (SFF) used for the HP Compaq dc7100 models and the Slim Tower (ST) used for the HP Comapq dx6100 models are shown in Figure 2-13. Features include:...
Page 33 System Overview Microtower Chassis Figure 2-14 shows the layout for the Microtower (MT) chassis used for the HP Compaq dx6100 models. Features include: Externally accessible drive bay assembly. Easy access to expansion slots and all socketed system board components. Item...
Page 34 Convertible Minitower Figure 2-15 shows the layout for the Convertible Minitower (CMT) chassis in the minitower configuration used for HP Compaq dc7100 models. Features include: Externally accessible drive bay assembly may be configured for minitower (vertical) or desktop (horizontal) position.
Page 35: Board Layouts
System Overview 2.3.3 Board Layouts Figures 2-16 through 2-18 show the system and expansion boards for these systems. Note: See USDT rear chassis illustrations for externally accessible I/O connectors. Item Description Item Description Hood sense header Power button, power LED, HD LED header Battery Front panel audio connector Parallel port option header...
Page 36 System Overview 3 4 5 6 7 8 Note: See SFF and ST rear chassis illustrations for externally accessible I/O connectors. Item Description Item Description Serial port B header Front panel audio header Battery Chassis speaker connector SATA #1 header Front panel USB port connector SATA #0 header MultiBay connector...
Page 37 System Overview PCI Expansion Board [1] System Board Item Description Item Description PCI 2.3 slots Serial ATA #2 connector [3] Battery Serial ATA #0 connector PCI Express x1 slot Hood lock header [3] PCI Express x16 graphics slot / normal layout SDVO slot [2] Hood sense header [3] Chassis fan header Password clear jumper header...
Page 38: System Architecture
System Overview 2.4 System Architecture The systems covered in this guide feature an architecture based on the Intel Pentium 4 processor and the Intel 915G chipset (Figure 2-11). These systems allow processor upgrading with the Intel Pentium 4 family and offer flexibility in expansion capabilities. All systems covered in this guide include the following key components: Intel Pentium 4 with Hyper-Threading technology, 32-KB L1 cache and 1-MB L2 cache.
Page 39 System Overview Pentium 4 Processor 915G/GV Chipset Graphics Ch A DDR Monitor Cntlr. SDRAM 915 [2] SDRAM GMCH Cntlr Ch B DDR PCI Exp. PCI Express SDRAM PEG I/F [1] x16 slot (PEG)[1] SATA SATA USB Ports 1-8 Hard Drive MultiBay Device Parallel I/F [1] Serial I/F [1]...
Page 40: Intel Pentium 4 Processor
System Overview 2.4.1 Intel Pentium 4 Processor The models covered in this guide feature the Intel Pentium 4 processor with Hyper-Threading technology. This processor is backward-compatible with software written for the Pentium III, Pentium II, Pentium MMX, Pentium Pro, Pentium, and x86 microprocessors. The processor architecture includes a floating-point unit, 32-KB first and 1-MB secondary caches, and enhanced performance for multimedia applications through the use of multimedia extension (MMX) instructions.
Page 41: Chipset
IDE I/F with SATA and PATA support AC ’97 controller RTC/CMOS IRQ controller Power management logic USB 1.1/2.0 controllers supporting eight (8) ports 82802 FWH [1] Loaded with HP/Compaq BIOS NOTE: [1] Or equivalent component. Technical Reference Guide 361834-001 2-25...
Page 42: Support Components
System Overview 2.4.3 Support Components Input/output functions not provided by the chipset are handled by other support components. Some of these components also provide “housekeeping” and various other functions as well. Table 2-4 shows the functions provided by the support components. Table 2-4 Support Component Functions Component Name...
Page 43: Mass Storage
System Overview 2.4.5 Mass Storage All models support at least two mass storage devices, with one being externally accessible for removable media. These systems provide one, two, or four SATA interfaces and one PATA interface. These systems may be preconfigured or upgraded with a 40-, 80-, or 160-GB SATA hard drive and one removable media drive such as a CD-ROM drive.
Page 44 System Overview 2.4.9 Graphics Subsystem These systems use the 82915G or 82915GV GMCH component that integrates an Intel graphics controller that can drive an external VGA monitor. The integrated graphics controller (IGC) features a 333-MHz core processor and a 400-MHz RAMDAC. The controller implements Dynamic Video Memory Technology (DVMT 3.0) for video memory.
Page 45 System Overview 2.5 Specifications This section includes the environmental, electrical, and physical specifications for the systems covered in this guide. Where provided, metric statistics are given in parenthesis. Specifications are subject to change without notice. Table 2-6 Environmental Specifications (Factory Configuration) Parameter Operating Non-operating...
Page 46 System Overview Table 2-8 Physical Specifications Parameter USDT CMT [3] Height 2.95 in 3.95 in 3.95 in 14.5 in 17.65 in (7.49 cm) (10.03 cm) (10.03 cm) (36.8 cm) (44.8 cm) Width 12.4 in 13.3 in 13.3 in 6.88 in 6.60 in (31.5 cm) (33.78 cm)
Page 47 System Overview Table 2-9 Diskette Drive Specifications Parameter Measurement Media Type 3.5 in 1.44 MB/720 KB diskette Height 1/3 bay (1 in) Bytes per Sector Sectors per Track: High Density Low Density Tracks per Side: High Density Low Density Read/Write Heads Average Access Time: Track-to-Track (high/low) 3 ms/6 ms...
Page 48 System Overview Table 2-10 Optical Drive Specifications Parameter 48x CD-ROM 48/24/28x CD-RW Drive Interface Type Media Type (reading) Mode 1,2, Mixed Mode, CD-DA, Mode 1,2, Mixed Mode, CD-DA, Photo CD, Cdi, CD-XA Photo CD, Cdi, CD-XA Media Type (writing) CD-R, CD-RW Transfer Rate (Reads) 4.8 Kb/s (max sustained) CD-ROM, 4.8 Kb/s;...
Page 49 System Overview Table 2-11 Hard Drive Specifications Parameter 40 GB 80 GB 160 GB Drive Size 3.5 in 3.5 in 3.5 in Interface SATA SATA SATA Transfer Rate 150 MB/s 150 MB/s 150 MB/s Drive Protection System Support? Typical Seek Time (w/settling) Single Track 1.2 ms 0.8 ms...
Page 50 System Overview 2-34 361834-001 Technical Reference Guide...
Page 51: Processor/Memory Subsystem
Processor/Memory Subsystem Introduction This chapter describes the processor/memory subsystem. These systems feature the Intel Pentium 4 processor and the 915G chipset (Figure 3-1). These systems support PC2700 or PC3200 DDR memory and come standard with PC3200 DIMMs installed. Pentium 4 Processor XMM1 XMM2 [1]...
Page 52: Pentium 4 Processor
Processor/Memory Subsystem 3.2 Pentium 4 Processor These systems each feature an Intel Pentium 4 processor in a FC-LGA775 package mounted with a passive heat sink in a zero-insertion force socket. The mounting socket allows the processor to be easily changed for servicing and/or upgrading. 3.2.1 Processor Overview The Intel Pentium 4 processor represents the latest generation of Intel's IA32-class of processors.
Page 53: Processor Upgrading
Processor/Memory Subsystem Figure 3-2 illustrates the internal architecture of the Intel Pentium 4 processor. Pentium 4 Processor Branch 16-K Execution 128-bit Prediction Trace Cache Integer 1-MB Adv.. Data Transfer Cache Cache Rapid Exe. Eng. Out-of-Order Core ALUs Core speed ALU Speed (Core speed x2) FSB speed (max.
Page 54: Memory Subsystem
The SPD format supported by these systems complies with the JEDEC specification for 128-byte EEPROMs. This system also provides support for 256-byte EEPROMs to include additional HP-added features such as part number and serial number. The SPD format as supported in this system (SPD rev. 1) is shown in Table 3-1.
Page 55 Processor/Memory Subsystem Table 3-1 shows suggested memory configurations for these systems. NOTE: Table 3-1 does not list all possible configurations. Balanced-capacity, dual-channel loading yields best performance. Table 3-1. DIMM Socket Loading Channel A Channel B Socket 1 Socket 2 [1] Socket 3 Socket 4 Total...
Page 56 [8] Field specified as optional by JEDEC but required by this system. [9] HP usage. This system requires that the DIMM EEPROM have this space available for reads/writes. [10] Serial # in ASCII format (MSB is 133). Intended as backup identifier in case vender data is invalid.
Page 57 Processor/Memory Subsystem Figure 3-3 shows the system memory map. 4 GB FFFF FFFFh High BIOS Area FFE0 0000h DMI/APIC Area F000 0000h Memory Area Top of DRAM IGC (1-32 MB) Main TSEG Memory Area Main Memory 0100 0000h 16 MB 00FF FFFFh Main Memory...
Page 58 Processor/Memory Subsystem 361834-001 Technical Reference Guide...
Page 59: System Support
System Support Introduction This chapter covers subjects dealing with basic system architecture and covers the following topics: PCI bus overview (4.2), page 4-1 System resources (4.3), page 4-11 Real-time clock and configuration memory (4.4), page 4-19 System management (4.5), page 4-21 Register map and miscellaneous functions (4.6), page 4-26 This chapter covers functions provided by off-the-shelf chipsets and therefore describes only basic aspects of these functions as well as information unique to the systems covered in this...
Page 60: Pci 2.3 Operation
System Support 82915G/GV [1] Integrated GMCH RGB Monitor Graphics Memory Controller Cntlr Function Host-PCI Exp. PCI Bus 0 PCI Express x16 graphics slot [2] Bridge Host-DMI Bridge DMI Link 82801 ICH6 PCI Bus 1 SATA USB I/F AC97 Cntlr Bridge Cntlr Cntlr Cntlr...
Page 61 System Support Configuration Cycles Devices on the PCI bus must comply with PCI protocol that allows configuration of that device by software. In this system, configuration mechanism #1 (as described in the PCI Local Bus specification Rev. 2.3) is employed. This method uses two 32-bit registers for initiating a configuration cycle for accessing the configuration space of a PCI device.
Page 62 System Support Table 4-1 shows the standard configuration of device numbers and IDSEL connections for components and slots residing on a PCI 2.3 bus. Table 4-1 PCI Component Configuration Access PCI Bus IDSEL PCI Component Notes Function # Device # Wired to: 82915G GMCH: Host/DMI Bridge...
Page 63 System Support The register index (CF8h, bits <7..2>) identifies the 32-bit location within the configuration space of the PCI device to be accessed. All PCI devices can contain up to 256 bytes of configuration data (Figure 4-3), of which the first 64 bytes comprise the configuration space header.
Page 64: Pci Express Bus Operation
System Support Table 4-3. PCI Bus Mastering Devices Device REQ/GNT Line Note PCI Connector Slot 1 REQ0/GNT0 PCI Connector Slot 2 REQ1/GNT1 PCI Connector Slot 3 REQ2/GNT2 PCI Connector Slot 4 REQ3/GNT3 NOTE: [1]SFF, ST, MT, and CMT form factors only. [2] CMT form factor with PCI expansion board PCI bus arbitration is based on a round-robin scheme that complies with the fairness algorithm specified by the PCI specification.
Page 65 System Support Link Layer The link layer provides data integrity by adding a sequence information prefix and a CRC suffix to the packet created by the transaction layer. Flow-control methods ensure that a packet will only be transferred if the receiving device is ready to accomodate it. A corrupted packet will be automatically re-sent.
Page 66: Option Rom Mapping
System Support For a PCI Express x16 transfer, a lane will be re-used every17th byte of a transfer. The mux-demux process provided by the physical layer is transparent to the other layers and to software/drivers. The SFF, ST, MT MT, and CMT forma factors provide two PCI Express slots: a PCI Express x16 (16-lane) slot specifically designed for a graphics controller, and a general purpose PCI Express x1 (1-lane) slot.
Page 67: Pci Connectors
System Support 4.2.6 PCI Connectors PCI 2.3 Connector Figure 4-5. PCI 2.3 Bus Connector (32-Bit, 5.0-volt Type) Table 4-5. PCI 2.3 Bus Connector Pinout B Signal A Signal B Signal A Signal B Signal A Signal -12 VDC TRST- AD28 +3.3 VDC +12 VDC AD27...
Page 68 System Support PCI Express Connectors x1 Connector x16 Connector Figure 4-6. PCI Express Bus Connectors Table 4-6. PCI Express Bus Connector Pinout B Signal A Signal B Signal A Signal B Signal A Signal +12 VDC PRSNT1# PERp3 PERn9 +12 VDC +12 VDC RSVD PERn3...
Page 69: System Resources
System Support 4.3 System Resources This section describes the availability and basic control of major subsystems, otherwise known as resource allocation or simply “system resources.” System resources are provided on a priority basis through hardware interrupts and DMA requests and grants. 4.3.1 Interrupts The microprocessor uses two types of hardware interrupts;...
Page 70 System Support 8259 Mode The 8259 mode handles interrupts IRQ0-IRQ15 in the legacy (AT-system) method using 8259-equivalent logic. Table 4-7 lists the standard source configuration for maskable interrupts and their priorities in 8259 mode. If more than one interrupt is pending, the highest priority (lowest number) is processed first.
Page 71 System Support APIC Mode The Advanced Programmable Interrupt Controller (APIC) mode provides enhanced interrupt processing with the following advantages: Eliminates the processor's interrupt acknowledge cycle by using a separate (APIC) bus Programmable interrupt priority Additional interrupts (total of 24) The APIC mode accommodates eight PCI interrupt signals (INTA-..INTH-) for use by PCI devices.
Page 72 System Support Maskable Interrupt processing is controlled and monitored through standard AT-type I/O-mapped registers. These registers are listed in Table 4-8. Table 4-8. Maskable Interrupt Control Registers I/O Port Register 020h Base Address, Int. Cntlr. 1 021h Initialization Command Word 2-4, Int. Cntlr. 1 0A0h Base Address, Int.
Page 73 System Support The NMI Status Register at I/O port 061h contains NMI source and status data as follows: NMI Status Register 61h Function NMI Status: 0 = No NMI from system board parity error. 1 = NMI requested, read only IOCHK- NMI: 0 = No NMI from IOCHK- 1 = IOCHK- is active (low), NMI requested, read only...
Page 74: Direct Memory Access
System Support 4.3.2 Direct Memory Access Direct Memory Access (DMA) is a method by which a device accesses system memory without involving the microprocessor. Although the DMA method has been traditionally used to transfer blocks of data to or from an ISA I/O device, PCI devices may also use DMA operation as well. The DMA method reduces the amount of CPU interactions with memory, freeing the CPU for other processing tasks.
Page 75 System Support DMA Page Registers The DMA page register contains the eight most significant bits of the 24-bit address and works in conjunction with the DMA controllers to define the complete (24-bit) address for the DMA channels. Table 4-10 lists the page register port addresses. Table 4-10.
Page 76 System Support The remaining address lines are in an undefined state during the refresh cycle. The refresh operations are driven by a 69.799-KHz clock generated by Interval Timer 1, Counter 1. The refresh rate is 128 refresh cycles in 2.038 ms. DMA Controller Registers Table 4-11 lists the DMA Controller Registers and their I/O port addresses.
Page 77: Real-Time Clock And Configuration Memory
System Support 4.4 Real-Time Clock and Configuration Memory The Real-time clock (RTC) and configuration memory (also referred to as “CMOS”) functions are provided by the 82801 component and is MC146818-compatible. As shown in the following figure, the 82801 ICH6 component provides 256 bytes of battery-backed RAM divided into two 128-byte configuration memory areas.
Page 78: Cmos Archive And Restore
System Support 4.4.2 CMOS Archive and Restore During the boot sequence the BIOS saves a copy of NVRAM (CMOS contents, password(s) and other system variables) in a portion of the flash ROM. Should the system become un-usable, the last good copy of NVRAM data can be restored with the Power Button Override function. This function is invoked with the following procedure: 1.
Page 79: Standard Cmos Locations
System Support 4.4.3 Standard CMOS Locations Table 4-12 describes standard configuration memory locations 0Ah-3Fh. These locations are accessible through using OUT/IN assembly language instructions using port 70/71h or BIOS function INT15, AX=E823h. Table 4-12. Configuration Memory (CMOS) Map Location Function Location Function 00-0Dh...
Page 80 System Support Power-On / Setup Password These systems include a power-on and setup passwords, which may be enabled or disabled (cleared) through a jumper on the system board. The jumper controls a GPIO input to the 82801 ICH6 that is checked during POST. The password is stored in configuration memory (CMOS) and if enabled and then forgotten by the user will require that either the password be cleared (preferable solution and described below) or the entire CMOS be cleared (refer to section 4.4.1).
Page 81: Power Management
System Support Level 0—Cover removal indication is essentially disabled at this level. During POST, status bit is cleared and no other action is taken by BIOS. Level 1—During POST the message “The computer's cover has been removed since the last system start up”...
Page 82: System Status
System Support 4.5.3 System Status These systems provide a visual indication of system boot and ROM flash status through the keyboard LEDs and operational status using bi-colored power and hard drive activity LEDs as indicated in Tables 4-13 and 4-14 respectively. The LED indications listed in Table 4-13 are valid only for PS/2-type keyboards.
Page 83: Thermal Sensing And Cooling
System Support 4.5.4 Thermal Sensing and Cooling All systems feature a variable-speed fan mounted as part of the processor heatsink assembly. All systems also provide or support an auxiliary chassis fan. All fans are controlled through temperature sensing logic on the system board and/or in the power supply. There are some electrical differences between form factors and between some models, although the overall functionally is the same.
Page 84: Register Map And Miscellaneous Functions
System Support 4.6 Register Map and Miscellaneous Functions This section contains the system I/O map and information on general-purpose functions of the ICH6 and I/O controller. 4.6.1 System I/O Map Table 4-15 lists the fixed addresses of the input/output (I/O) ports. Table 4-15 System I/O Map I/O Port...
Page 85: Lpc47B397 I/O Controller Functions
System Support 4.6.2 LPC47B397 I/O Controller Functions The LPC47B397 I/O controller contains various functions such as the keyboard/mouse interfaces, diskette interface, serial interfaces, and parallel interface. While the control of these interfaces uses standard AT-type I/O addressing (as described in chapter 5) the configuration of these functions uses indexed ports unique to the LPC47B397.
Page 86 System Support The configuration registers are accessed through I/O registers 2Eh (index) and 2Fh (data) after the configuration phase has been activated by writing 55h to I/O port 2Eh. The desired interface (logical device) is initiated by firmware selecting logical device number of the 47B347 using the following sequence: 1.
Page 87: Input/Output Interfaces
Input/Output Interfaces Introduction This chapter describes the standard (i.e., system board) interfaces that provide input and output (I/O) porting of data and specifically discusses interfaces that are controlled through I/O-mapped registers. The following I/O interfaces are covered in this chapter: PATA/SATA interface (5.2), page 5-1 Diskette drive interface (5.3), page 5-7 Serial interfaces (5.4), page 5-12...
Page 88 Input/Output Interfaces IDE Configuration Registers The IDE controller is configured as a PCI device with bus mastering capability. The PCI configuration registers for the IDE controller function (PCI device #31, function #1) are listed in Table 5-1. Table 5-1. EIDE PCI Configuration Registers (82801) Reset PCI Conf.
Page 89 Input/Output Interfaces IDE Bus Master Control Registers The IDE interface can perform PCI bus master operations using the registers listed in Table 5-2. These registers occupy 16 bytes of variable I/O space set by software and indicated by PCI configuration register 20h in the previous table. Table 5-2.
Page 90 Input/Output Interfaces Table 5-3. 40-Pin IDE (PATA) Connector Pinout Signal Description Signal Description RESET- Reset DMA Request Ground Ground Data Bit <7> IOW- I/O Write [1] Data Bit <8> Ground Data Bit <6> IOR- I/O Read [2] Data Bit <9> Ground Data Bit <5>...
Page 91 Input/Output Interfaces SATA Interfaces These systems provide one, two, or four serial ATA (SATA) interfaces that can provide certain advantages over legacy EIDE (PATA) interface including: Higher transfer rates: up to 1.5 Gb/s (150 MB/s) Reduced wiring (smaller cable assemblies) The SATA interface duplicates most of the functionality of the EIDE interface through a register interface that is equivalent to that of the legacy IDE host adapter.
Page 92 Input/Output Interfaces SATA Bus Master Control Registers The SATA interface can perform PCI bus master operations using the registers listed in Table 5-5. These registers occupy 16 bytes of variable I/O space set by software and indicated by PCI configuration register 20h in the previous table. As indicated, these registers are virtually a copy of those used by EIDE operations discussed in the EIDE section.
Page 93: Diskette Drive Interface
Input/Output Interfaces 5.3 Diskette Drive Interface The diskette drive interface in these systems support one diskette drive connected to a standard 34-pin diskette drive connector. Selected models come standard with a 3.5-inch 1.44-MB diskette drive installed as drive A. The diskette drive interface function is integrated into the LPC47B397 super I/O component. The internal logic of the I/O controller is software-compatible with standard 82077-type logic.
Page 94 Input/Output Interfaces Table 5-7. Diskette Drive Interface Configuration Registers Index Reset Address Function Value Activate 60-61h Base Address 03F0h Interrupt Select DMA Channel Select DD Mode DD Option DD Type DD 0 DD 1 For detailed configuration register information refer to the SMSC data sheet for the LPC47B397 I/O component.
Page 95 Input/Output Interfaces Diskette Drive Interface Control The BIOS function INT 13 provides basic control of the diskette drive interface. The diskette drive interface can be controlled by software through the LPC47B397's I/O-mapped registers listed in Table 5-8. The diskette drive controller of the LPC47B397 operates in the PC/AT mode in these systems.
Page 96 Input/Output Interfaces Table 5-8. (Continued) Diskette Drive Interface Control Registers Primary Second. Address Address Register 3F4h 374h Main Status Register (MSR): <7> Request for master (host can transfer data) (active high) <6> Transfer direction (0 – write, 1 = read) <5>...
Page 97: Diskette Drive Connector
Input/Output Interfaces 5.3.2 Diskette Drive Connector This system uses a standard 34-pin connector (refer to Figure 5-3 and Table 5-9 for the pinout) for diskette drives. Drive power is supplied through a separate connector. Figure 5-3. 34-Pin Diskette Drive Connector. Table 5-9.
Page 98: Serial Interface
Input/Output Interfaces 5.4 Serial Interface Systems covered in this guide may include one RS-232-C type serial interface to transmit and receive asynchronous serial data with external devices. Some systems may allow the installation of a second serial interface through an adapter that consists of a PCI bracket and a cable that attaches to header P52 on the system board.
Page 99 Input/Output Interfaces The serial interface configuration registers are listed in the following table: Table 5-11. Serial Interface Configuration Registers Index Address Function Activate Base Address MSB Base Address LSB Interrupt Select Mode Register Serial Interface Control The BIOS function INT 14 provides basic control of the serial interface. The serial interface can be directly controlled by software through the I/O-mapped registers listed in Table 5-12.
Page 100: Parallel Interface
Input/Output Interfaces 5.5 Parallel Interface Systems covered in this guide may include a parallel interface for connection to a peripheral device with a compatible interface, the most common being a printer. The parallel interface function is integrated into the LPC47B397 I/O controller component and provides bi-directional 8-bit parallel data transfers with a peripheral device.
Page 101: Extended Capabilities Port Mode
Input/Output Interfaces 5.5.3 Extended Capabilities Port Mode The Extended Capabilities Port (ECP) mode, like EPP, also uses a hardware protocol-based design that supports transfers up to 2 MB/s. Automatic generation of addresses and strobes as well as Run Length Encoding (RLE) decompression is supported by ECP mode. The ECP mode includes a bi-directional FIFO buffer that can be accessed by the CPU using DMA or programmed I/O.
Page 102 Input/Output Interfaces Parallel Interface Control The BIOS function INT 17 provides simplified control of the parallel interface. Basic functions such as initialization, character printing, and printer status are provide by subfunctions of INT 17. The parallel interface is controllable by software through a set of I/O mapped registers. The number and type of registers available depends on the mode used (SPP, EPP, or ECP).
Page 103: Parallel Interface Connector
Input/Output Interfaces 5.5.5 Parallel Interface Connector Figure 5-5 and Table 5-15 show the connector and pinout of the parallel interface connector. Note that some signals are redefined depending on the port's operational mode. Figure 5-5. Parallel Interface Connector (Female DB-25 as viewed from rear of chassis) Table 5-15.
Page 104: Keyboard/Pointing Device Interface
Input/Output Interfaces 5.6 Keyboard/Pointing Device Interface The keyboard/pointing device interface function is provided by the LPC47B397 I/O controller component, which integrates 8042-compatible keyboard controller logic (hereafter referred to as simply the “8042”) to communicate with the keyboard and pointing device using bi-directional serial data transfers.
Page 105 Input/Output Interfaces Table 5-16 lists and describes commands that can be issued by the 8042 to the keyboard. Table 5-16. 8042-To-Keyboard Commands Command Value Description Set/Reset Status Indicators Enables LED indicators. Value EDh is followed by an option byte that specifies the indicator as follows: Bits <7..3>...
Page 106: Pointing Device Interface Operating
Input/Output Interfaces Table 5-16. (Continued) 8042-To-Keyboard Commands Command Value Description Set Keys—Make/Brake Clears keyboard buffer and sets default scan code set. [1] Set Keys—Make Clears keyboard buffer and sets default scan code set. [1] Set Keys— Clears keyboard buffer and sets default scan code set. [1] Typematic/Make/Brake Set Type Key—Typematic Clears keyboard buffer and prepares to receive key ID.
Page 107 Input/Output Interfaces The keyboard interface configuration registers are listed in the following table: Table 5-17. Keyboard Interface Configuration Registers Index Address Function Activate Primary Interrupt Select Secondary Interrupt Select Reset and A20 Select 8042 Control The BIOS function INT 16 is typically used for controlling interaction with the keyboard. Sub-functions of INT 16 conduct the basic routines of handling keyboard data (i.e., translating the keyboard's scan codes into ASCII codes).
Page 108 Input/Output Interfaces I/O Port 64h I/O port 64h is used for reading the status register and for writing commands. A read of 64h by the CPU will yield the status byte defined as follows: Function 7..4 General Purpose Flags. CMD/DATA Flag (reflects the state of A2 during a CPU write). 0 = Data 1 = Command General Purpose Flag.
Page 109 Input/Output Interfaces Table 5-18. (Continued) CPU Commands to the 8042 Value Command Description Test the clock and data lines of the pointing device interface and place test results in the output buffer. 00h = No error detected 01h = Clock line stuck low 02h = Clock line stuck high 03h = Data line stuck low 04h = Data line stuck high...
Page 110: Keyboard/Pointing Device Interface Connector
Input/Output Interfaces 5.6.4 Keyboard/Pointing Device Interface Connector The legacy-light model provides separate PS/2 connectors for the keyboard and pointing device. Both connectors are identical both physically and electrically. Figure 5-7 and Table 5-19 show the connector and pinout of the keyboard/pointing device interface connectors. Figure 5-7.
Page 111: Universal Serial Bus Interface
Input/Output Interfaces 5.7 Universal Serial Bus Interface The Universal Serial Bus (USB) interface provides asynchronous/isochronous data transfers with compatible peripherals such as keyboards, printers, or modems. This high-speed interface supports hot-plugging of compatible devices, making possible system configuration changes without powering down or even rebooting systems. As shown in Figure 5-8, the USB interface is provided by the 82801 component.
Page 112: Usb Data Formats
Input/Output Interfaces 5.7.1 USB Data Formats The USB I/F uses non-return-to-zero inverted (NRZI) encoding for data transmissions, in which a 1 is represented by no change (between bit times) in signal level and a 0 is represented by a change in signal level. Bit stuffing is employed prior to NRZ1 encoding so that in the event a string of 1's is transmitted (normally resulting in a steady signal level) a 0 is inserted after every six consecutive 1's to ensure adequate signal transitions in the data stream.
Page 113: Usb Programming
Input/Output Interfaces 5.7.2 USB Programming Programming the USB interface consists of configuration, which typically occurs during POST, and control, which occurs at runtime. USB Configuration Each USB controller functions as a PCI device within the 82801 component and is configured using PCI Configuration Registers as listed in Table 5-20.
Page 114: Usb Connector
Input/Output Interfaces USB Control The USB is controlled through I/O registers as listed in table 5-21. Table 5-21. USB Control Registers I/O Address Register Default Value 00, 01h Command 0000h 02, 03h Status 0000h 04, 05h Interupt Enable 0000h 06, 07 Frame Number 0000h 08, 0B...
Page 115: Usb Cable Data
Input/Output Interfaces 5.7.4 USB Cable Data The recommended cable length between the host and the USB device should be no longer than sixteen feet for full-channel (12 MB/s) operation, depending on cable specification (see following table). Table 5-23. USB Cable Length Data Conductor Size Resistance Maximum Length...
Page 116: Audio Subsystem
7056 Line In AUX In Header P11 [1] Aux Audio (L) Spkr Mute Audio Aux Audio (R) Codec HP Out Audio (L/R) Headphones/ Line Out CD ROM Header P7 [2] CD Audio (L) CD Audio (R) Audio Bias Mic In Figure 5-11.
Page 117: Ac97 Audio Controller
Input/Output Interfaces 5.8.1 AC97 Audio Controller The AC97 Audio Controller is a PCI device that is integrated into the 82801 ICH component and supports the following functions: Read/write access to audio codec registers 16-bit stereo PCM output @ up to 48 KHz sampling 16-bit stereo PCM input @ up to 48 KHz sampling Acoustic echo correction for microphone AC'97 Link Bus...
Page 118: Audio Codec
Sample Rate Σ/Mixer AC97 Gen. Audio Link Controller SPDIF Data (L) HP Out L Gain Analog SD Out Output HP Out R Circuits Data (R) Gain Figure 5-13. AD1981B Audio Codec Functional Block Diagram All inputs and outputs are two-channel stereo except for the microphone input, which is inputted as a single-channel but mixed internally onto both left and right channels.
Page 119: Audio Programming
Input/Output Interfaces 5.8.4 Audio Programming Audio subsystem programming consists configuration, typically accomplished during POST, and control, which occurs during runtime. Audio Configuration The audio subsystem is configured according to PCI protocol through the AC97 audio controller function of the 82801 ICH. Table 5-24 lists the PCI configuration registers of the audio subsystem.
Page 120 Input/Output Interfaces Audio Control The audio subsystem is controlled through a set of indexed registers that physically reside in the audio codec . The register addresses are decoded by the audio controller and forwarded to the audio codec over the AC97 Link Bus previously described. The audio codec's control registers (Table 5-25) are mapped into 64 kilobytes of variable I/O space.
Page 121: Audio Specifications
Input/Output Interfaces 5.8.5 Audio Specifications The specifications for the integrated AC97 audio subsystem are listed in Table 5-26. Table 5-26. AC97 Audio Subsystem Specifications Parameter Measurement Sampling Rate 7040 KHz to 48 KHz Resolution 16 bit Nominal Input Voltage: Mic In (w/+20 db gain) .283 Vp-p Line In 2.83 Vp-p...
Page 122: Network Interface Controller
Input/Output Interfaces 5.9 Network Interface Controller These systems provide 10/100/1000 Mbps network support through a Broadcom BCM5751 network interface controller (NIC), a PHY component, and a RJ-45 jack with integral status LEDs. The 82562-equivalent controller integrated into the 82801 ICH component is not used (disabled) in these systems.
Page 123: Wake-On-Lan Support
Input/Output Interfaces 5.9.1 Wake-On-LAN Support The NIC supports the Wired-for-Management (WfM) standard of Wake-On-LAN (WOL) that allows the system to be booted up from a powered-down or low-power condition upon the detection of special packets received over a network. The NIC receives 3.3 VDC auxiliary power while the system unit is powered down in order to process special packets.
Page 124: Nic Programming
The Broadcom BCM5782 is configured as a PCI device and controlled through registers mapped in variable I/O space. The BIOS for the BCM5782 is contained within the HP/Compaq BIOS in system ROM. Refer to Broadcom documentation for details regarding BCM5782 register programming.
Page 125: Nic Specifications
Input/Output Interfaces 5.9.6 NIC Specifications Table 5-27. NIC Specifications Parameter Modes Supported 10BASE-T half duplex @ 10 Mb/s 10Base-T full duplex @ 20 Mb/s 100BASE-TX half duplex @ 100 Mb/s 100Base-TX full duplex @ 200 Mb/s 1000BASE-T half duplex @ 1 Gb/s 1000BASE-TX full duplex @ 2 Gb/s Standards Compliance IEEE 802.2...
Page 126 Input/Output Interfaces 5-40 361834-001 Technical Reference Guide...
Page 127: Graphics Subsystem
Integrated Graphics Subsystem Introduction This chapter describes graphics subsystem that is integrated into the 82915G/GV GMCH component. This graphics subsystem employs the use of system memory to provide efficient, economical 2D and 3D performance. The SFF, ST, MT, and CMT form factors may be upgraded by installing a graphics card into the PCI Express x16 or the PCI 2.3 slot.
Page 128: Functional Description
Integrated Graphics Subsystem 6.2 Functional Description The Intel 915G/GV GMCH component includes an integrated graphics controller (IGC). (Figure 6-1). The IGC can directly drive an external, analog multi-scan monitor at resolutions up to and including 2048 x 1536 pixels. The IGC includes a memory management feature that allocates portions of system memory for use as the frame buffer and for storing textures and 3D effects.
Page 129 Integrated Graphics Subsystem The graphics controller integrated into the 82915G/GV GMCH component includes 2D and 3D accelerator engines working with a deeply-pipelined pre-processor. Hardware cursor and overlay generators are also included as well as a legacy VGA processor core. The IGC supports three display devices: One progressive-scan analog monitor Up to two additional video displays with the installation of an optional Advanced Digital...
Page 130: Video Memory Allocation Reporting
Integrated Graphics Subsystem 6.2.1 Video Memory Allocation Reporting The IGC does not have local memory at its disposal but instead uses a portion of system memory allocated for frame buffering and texturing. The total memory allocation is determined by the amount of system memory installed in a system.
Page 131: Display Modes
Integrated Graphics Subsystem 6.3 Display Modes The IGC supports most standard display modes for 2D video displays up to and including 2048 x 1536 @ 85 Hz , and 3D display modes up to 1600 x 1200 @ 85 Hz. The highest resolution available will be determined by the following factors: Memory speed and amount Single or dual channel memory...
Page 132: Vga Monitor Connector
Integrated Graphics Subsystem 6.5 VGA Monitor Connector These systems includes a standard VGA connector (Figure 6-3) for attaching an analog monitor: Figure 6 3. VGA Monitor Connector, (Female DB-15, as viewed from rear). Table 6-1. DB-15 Monitor Connector Pinout Signal Description Signal Description...
Page 133: Power And Signal Distribution
Power and Signal Distribution Introduction This chapter describes the power supply and method of general power and signal distribution. Topics covered in this chapter include: Power supply assembly/control (7.2), page 7-1 Power distribution (7.3), page 7-8 Signal distribution (7.4), page 7-13 Power Supply Assembly/Control These systems feature a power supply assembly that is controlled through programmable logic (Figure 7-1).
Page 134: Power Supply Assembly
Power and Signal Distribution 7.2.1 Power Supply Assembly These systems feature power supplies with power factor-correction logic. Four power supplies are used: a 200-watt power supply for the USDT unit, a 240-watt power supply for the SFF and ST units, a 300-watt power supply for the MT unit, and a 340-watt power supply for the CMT unit.
Page 135 Power and Signal Distribution Table 7-3. 300-Watt (MT) Power Supply Assembly Specifications Min. Range/ Current Max. Surge Max. Tolerance Loading [1] Current Current [2] Ripple Input Line Voltage: 115 VAC Setting 90 - 132 VAC 230 VAC Setting 180 - 264 VAC Line Frequency 47–63 Hz Constant Input (AC) Current...
Page 136: Power Control
Power and Signal Distribution 7.2.2 Power Control The power supply assembly is controlled digitally by the PS On signal (Figure 7-1). When PS On is asserted, the Power Supply Assembly is activated and all voltage outputs are produced. When PS On is de-asserted, the Power Supply Assembly is off and no voltages (except +5 AUX) are generated.
Page 137 Power and Signal Distribution Power LED Indications A dual-color LED located on the front panel (bezel) is used to indicate system power status. The front panel (bezel) power LED provides a visual indication of key system conditions listed as follows: Power LED Condition Steady green...
Page 138 Power and Signal Distribution The wake up sequence for each event occurs as follows: Wake-On-LAN The network interface controller (NIC) can be configured for detection of a “Magic Packet” and wake the system up from sleep mode through the assertion of the PME- signal on the PCI bus. Refer to Chapter 5, “Network Support”...
Page 139: Power Management
Power and Signal Distribution 7.2.3 Power Management These systems include power management functions designed to conserve energy. These functions are provided by a combination of hardware, firmware (BIOS) and software. The system provides the following power management features: ACPI v1.0b compliant (ACPI modes C1, C2, S1, and S3, ) APM 1.2 compliant U.S.
Page 140: Power Distribution
Power and Signal Distribution Power Distribution 7.3.1 3.3/5/12 VDC Distribution The power supply assembly includes a multi-connector cable assembly that routes +3.3 VDC, +5 VDC, +5 VDC STB, +12 VC, and -12 VDC to the system board as well as to the individual drive assemblies.
Page 141 Power and Signal Distribution Figure 7-3 shows the power supply cabling for the SFF/ST systems. 1 2 3 4 P4, P5 Power Supply 349318 Conn Pin 1 Pin 2 Pin 3 Pin 4 Pin 5 Pin 6 Pin 7 Pin 8 Pin 9 PS On Pwr Gd...
Page 142 Power and Signal Distribution Figure 7-4 shows the power supply cabling for the microtower systems. P9, P10 P4 P9 P5 P10 P2, P3, P4, P5, P6 Power Supply 1 2 3 4 366307 Conn Pin 1 Pin 2 Pin 3 Pin 4 Pin 5 Pin 6...
Page 143 Power and Signal Distribution Figure 7-4 shows the power supply cabling for the convertible minitower systems. P4, P5, P9, P10 P6, P7, P11 Power Supply 1 2 3 4 349774 Conn Pin 1 Pin 2 Pin 3 Pin 4 Pin 5 Pin 6 Pin 7 Pin 8...
Page 144: Low Voltage Production/Distribution
Power and Signal Distribution 7.3.2 Low Voltage Production/Distribution Auxiliary voltages less than 5 volts and all voltages less than 3.3 volts are produced through regulator circuitry (Figure 7-6) on the system board. 5 Aux 3.3 Aux Power Supply DIMMs 2.5 VDC DIMMs 1.5 VDC DIMMs...
Page 145: Signal Distribution
Diskette Drive MultiBay CD Audio Daughter Board Keyboard Kybd data Mouse Mouse data Mic In, HP Out Audio Front Panel USB 6,7 Tx/Rx I/O Module NOTES: See Figure 7-10 for header pinout. Figure 7-7. USDT Form Factor Signal Distribution Diagram...
Page 146 Hard Drive 356033-001 CD-ROM IDE I/F Keyboard Kybd data Mouse Mouse data Mic In, HP Out Audio Front Panel USB 6,7 Tx/Rx I/O Module NOTES: See Figure 7-7 for header pinout. Figure 7-8. SFF / ST Form Factor Signal Distribution Diagram...
Page 147 Board Hard Drive xxxxxx-001 CD-ROM IDE I/F. Keyboard Kybd data Mouse Mouse data CD Audio Mic In, HP Out Audio Front Panel USB 6,7 Tx/Rx I/O Module PCI 2.3 I/F PCI Expansion Daughter Board [1] Notes: [1] Applicable to CMT form factor only.
Page 148 Power and Signal Distribution Power Button/LED, HD LED Power Button/LED, HD LED Header P5 (USDT, SFF, ST) Header P5 (MT, CMT) HD LED Cathode 1 2 PS LED Cathode HD LED Cathode 1 2 PS LED Cathode HD LED Anode 3 4 PS LED Anode HD LED Anode 3 4 PS LED Anode...
Page 149 BIOS ROM Introduction The Basic Input/Output System (BIOS) of the computer is a collection of machine language programs stored as firmware in read-only memory (ROM). The BIOS ROM includes such functions as Power-On Self Test (POST), PCI device initialization, Plug 'n Play support, power management activities, and the Setup utility.
Page 150: Bios Rom
All BIOS ROM upgrades are available directly from HP. Flashing is done either locally with the HP-provided Windows program, a ROMPaq diskette or remotely using the network boot function (described in the section 8.3.2).
Page 151: Changeable Splash Screen
A corrupted splash screen may be restored by the user with the ROMPAQ software. Depending on the system, changing (customizing) the splash screen may only be available with asistance from HP. The splash screen (image displayed during POST) is stored in the BIOS ROM and may be replaced with another image of choice by using the Image Flash utility (Flashi.exe).
Page 152: Network Boot (F12) Support
BIOS ROM 8.3.2 Network Boot (F12) Support The BIOS supports booting the system to a network server. The function is accessed by pressing the F12 key when prompted at the lower right hand corner of the display during POST. Booting to a network server allows for such functions as: Flashing a ROM on a system without a functional operating system (OS).
Page 153: Boot Error Codes
BIOS ROM 8.3.4 Boot Error Codes The BIOS provides visual and audible indications of a failed system boot by using the LEDS on the PS/2 keyboard and the system board speaker. The error conditions are listed in the following table. Table 8-2 Boot Error Codes Visual [1]...
Page 154: Setup Utility
BIOS ROM 8.4 Setup Utility The Setup utility (stored in ROM) allows the user to configure system functions involving security, power management, and system resources. The Setup utility is ROM-based and invoked when the key is pressed and held during the computer boot cycle. Highlights of the Setup utility are described in the following table.
Page 155 BIOS ROM Table 8-3 Setup Utility Heading Option Description File Save Changes and Saves changes to system configuration or default settings and exits (continued) Exit Computer Setup. Storage Device Lists all installed BIOS-controlled storage devices. Configuration When a device is selected, detailed information and options are displayed.
Page 156 BIOS ROM Table 8-3 Setup Utility Heading Option Description Translation Parameters (ATA disks only) This feature appears only when User translation mode is selected. Allows you to specify the parameters (logical cylinders, heads, and sectors per track) used by the BIOS to translate disk I/O requests (from the operating system or an application) into terms the hard drive can accept.
Page 157 BIOS ROM Table 8-3 Setup Utility Heading Option Description Secondary SATA Controller Allows you to enable or disable the Secondary SATA controller. This feature is supported on select models only. DPS Self-Test Allows you to execute self-tests on ATA hard drives capable of performing the Drive Protection System (DPS) self-tests.
Page 158 BIOS ROM Table 8-3 Setup Utility Heading Option Description Smart Cover Allows you to: • Lock/unlock the Cover Lock. • Set the Cover Removal Sensor to Disable/Notify User/Setup Password. Notify User alerts the user that the sensor has detected that the cover has been removed.
Page 159 BIOS ROM Table 8-3 Setup Utility Heading Option Description DriveLock Security Allows you to assign or modify a master or user password for MultiBay hard drives. When this feature is enabled, the user is prompted to provide one of the DriveLock passwords during POST. If neither is successfully entered, the hard drive will remain inaccessible until one of the passwords is successfully provided during a subsequent cold-boot sequence.
Page 160 BIOS ROM Table 8-3 Setup Utility Heading Option Description Restore Master Restores the backup Master Boot Record to the current bootable Boot Record* disk. Only appears if all of the following conditions are true: MBR Security is enabled. A backup copy of the MBR has been previously saved. The current bootable disk is the same disk from which the backup copy of the MBR was saved.
Page 161 BIOS ROM Table 8-3 Setup Utility Heading Option Description Advanced* Power-On Options Allows you to set: *For • POST mode (QuickBoot, FullBoot, or FullBoot every 1-30 days). advanced • POST messages (enable/disable). users only • F9 prompt (enable/disable). Enabling this feature will display the text F9=Boot Menu during POST.
Page 162 BIOS ROM Table 8-3 Setup Utility Heading Option Description Advanced* Power-On Options Allows you to set: (continued) (continued) (continued) • ACPI/USB Buffers @ Top of Memory (enable/disable). *For Enabling this feature places USB memory buffers at the top advanced of memory. The advantage is that some amount of memory users only below 1 MB is freed up for use by option ROMs.
Page 163 BIOS ROM Table 8-3 Setup Utility Heading Option Description Advanced* Device options Allows you to set: (continued) • Printer mode (bi-directional, EPP & ECP, output only). *For • Num Lock state at power-on (off/on). advanced • S5 Wake on LAN (enable/disable). users only •...
Page 164: Client Management Functions
BIOS ROM 8.5 Client Management Functions Table 8-4 provides a partial list of the client management BIOS functions supported by the systems covered in this guide. These functions, designed to support intelligent manageability applications, are Compaq-specific unless otherwise indicated. Table 8-4. Client Management Functions (INT15) Function Mode...
Page 165: System Id And Rom Type
BIOS ROM 8.5.1 System ID and ROM Type Diagnostic applications can use the INT 15, AX=E800h BIOS function to identify the type of system. This function will return the system ID in the BX register. systems have the following IDs and ROM family types: Table 8-5 System ID System (Form Factor)
Page 166: Pnp Support
BIOS ROM 8.6 PnP Support The BIOS includes Plug 'n Play (PnP) support for PnP version 1.0A. Table 8-6 lists the PnP functions supported. Table 8-6. PnP BIOS Functions Function Register Get number of system device nodes Get system device node Set system device node Get event Send message...
Page 167: Smbios
BIOS ROM 8.6.1 SMBIOS In support of the DMI specification the PnP functions 50h and 51h are used to retrieve the SMBIOS data. Function 50h retrieves the number of structures, size of the largest structure, and SMBIOS version. Function 51h retrieves a specific structure. This system supports SMBIOS version 2.3.1 and the following structure types: Type Data...
Page 168 BIOS ROM 8-20 361834-001 Technical Reference Guide...
Page 169 This appendix lists the error codes and a brief description of the probable cause of the error. Errors listed in this appendix are applicable only for systems running HP/Compaq BIOS. Not all errors listed in this appendix may be applicable to a particular system model and/or configuration.
Page 170 Error Messages and Codes A.3 Power-On Self Test (POST) Messages Table A-2. Power-On Self Test (POST) Messages Error Message Probable Cause Invalid Electronic Serial Number Chassis serial number is corrupt. Use Setup to enter a valid number. Network Server Mode Active (w/o System is in network mode.
Page 171 Error Messages and Codes Table A-2. (Continued) Power-On Self Test (POST) Messages Error Message Probable Cause 512-Chassis Fan Not Detected Chassis fan is not connected. 514-CPU or Chassis Fan not CPU fan is not connected or may have malfunctioned. detected. 601-Diskette Controller Error Diskette drive removed since previous boot.
Page 172 Error Messages and Codes Table A-2. (Continued) Power-On Self Test (POST) Messages Error Message Probable Cause 1794-Inaccessible devices A device is attached to SATA 1 and/or SATA 3. attached to SATA 1 and/or SATA 3 Devices attached to these connectors will be inaccessible while “SATA (for systems with 4 SATA ports) Emulation”...
Page 173 Error Messages and Codes A.4 System Error Messages (1xx-xx) Table A-3. System Error Messages Message Probable Cause Message Probable Cause Option ROM error 109-02 CMOS clock rollover test failed System board failure 109-03 CMOS not properly initialized (clk test) System board failure 110-01 Programmable timer load data test failed 104-01...
Page 174 Error Messages and Codes A.5 Memory Error Messages (2xx-xx) Table A-4. Memory Error Messages Message Probable Cause 200-04 Real memory size changed 200-05 Extended memory size changed 200-06 Invalid memory configuration 200-07 Extended memory size changed 200-08 CLIM memory size changed 201-01 Memory machine ID test failed 202-01...
Page 175 Error Messages and Codes Table A-4. (Continued) Memory Error Messages Message Probable Cause 211-02 Error while saving memory during random memory pattern test 211-03 Error while restoring memory during random memory pattern test 213-xx Incompatible DIMM in slot x 214-xx Noise test failed 215-xx Random address test...
Page 176 Error Messages and Codes A.7 Printer Error Messages (4xx-xx) Table A-6 Printer Error Messages Message Probable Cause Message Probable Cause 401-01 Printer failed or not connected 402-11 Interrupt test, data/cntrl. reg. failed 402-01 Printer data register failed 402-12 Interrupt test and loopback test failed 402-02 Printer control register failed 402-13...
Page 177 Error Messages and Codes A.9 Diskette Drive Error Messages (6xx-xx) Table A-8. Diskette Drive Error Messages Message Probable Cause Message Probable Cause 6xx-01 Exceeded maximum soft error limit 6xx-20 Failed to get drive type 6xx-02 Exceeded maximum hard error 6xx-21 Failed to get change line status limit 6xx-03...
Page 178 Error Messages and Codes A.10 Serial Interface Error Messages (11xx-xx) Table A-9. Serial Interface Error Messages Message Probable Cause Message Probable Cause 1101-01 UART DLAB bit failure 1101-13 UART cntrl. signal interrupt failure 1101-02 Line input or UART fault 1101-14 DRVR/RCVR data failure 1101-03 Address line fault...
Page 179 Error Messages and Codes A.11 Modem Communications Error Messages (12xx-xx) Table A-10. Modem Communications Error Messages Message Probable Cause Message Probable Cause 1201-XX Modem internal loopback test 1204-03 Data block retry limit reached [4] 1201-01 UART DLAB bit failure 1204-04 RX exceeded carrier lost limit 1201-02 Line input or UART failure...
Page 180 Error Messages and Codes Table A-10. (Continued) Modem Communications Error Messages Message Probable Cause Message Probable Cause 1202-13 Data block retry limit reached [2] 1210-01 Time-out waiting for SYNC [6] 1202-21 Time-out waiting for SYNC [3] 1210-02 Time-out waiting for response [6] 1202-22 Time-out waiting for response [3] 1210-03...
Page 181 Error Messages and Codes A.13 Hard Drive Error Messages (17xx-xx) Table A-12 Hard Drive Error Messages Message Probable Cause Message Probable Cause 17xx-01 Exceeded max. soft error limit 17xx-51 Failed I/O read test 17xx-02 Exceeded max. Hard error limit 17xx-52 Failed file I/O compare test 17xx-03 Previously exceeded max.
Page 182 Error Messages and Codes NOTE: xx = 00, Hard drive ID test xx = 19, Hard drive power mode test xx = 01, Hard drive format test xx = 20, SMART drive detects imminent failure xx = 02, Hard drive read test xx = 21, SCSI hard drive imminent failure xx = 03, Hard drive read/write compare test xx = 24, Net work preparation test xx = 04, Hard drive random seek test...
Page 183 Error Messages and Codes A.14 Hard Drive Error Messages (19xx-xx) Table A-13 Hard Drive Error Messages Message Probable Cause Message Probable Cause 19xx-01 Drive not installed 19xx-21 Got servo pulses second time but not first 19xx-02 Cartridge not installed 19xx-22 Never got to EOT after servo check 19xx-03 Tape motion error...
Page 184 Error Messages and Codes A.15 Video (Graphics) Error Messages (24xx-xx) Table A-14 Video (Graphics) Error Messages Message Probable Cause Message Probable Cause 2402-01 Video memory test failed 2418-02 EGA shadow RAM test failed 2403-01 Video attribute test failed 2419-01 EGA ROM checksum test failed 2404-01 Video character set test failed 2420-01...
Page 185 Error Messages and Codes A.17 DVD/CD-ROM Error Messages (33xx-xx) Table A-16 DVD/CD-ROM Error Messages Message Probable Cause 3301-xx Drive test failed 3305-xx Seek test failed A.18 Network Interface Error Messages (60xx-xx) Table A-17 Network Interface Error Messages Message Probable Cause Message Probable Cause 6000-xx...
Page 186 Error Messages and Codes A.19 SCSI Interface Error Messages (65xx-xx, 66xx-xx, 67xx-xx) Table A-18 SCSI Interface Error Messages Message Probable Cause Message Probable Cause 6nyy-02 Drive not installed 6nyy-33 Illegal controller command 6nyy-03 Media not installed 6nyy-34 Invalid SCSI bus phase 6nyy-05 Seek failure 6nyy-35...
Page 187 Error Messages and Codes A.20 Pointing Device Interface Error Messages (8601-xx) Table A-19 Pointing Device Interface Error Messages Message Probable Cause Message Probable Cause 8601-01 Mouse ID fails 8601-07 Right block not selected 8601-02 Left mouse button is inoperative 8601-08 Timeout occurred 8601-03 Left mouse button is stuck closed...
Page 188 Error Messages and Codes A-20 361834-001 Technical Reference Guide...
Page 189 ASCII Character Set B.1 Introduction This appendix lists, in Table B-1, the 256-character ASCII code set including the decimal and hexadecimal values. All ASCII symbols may be called while in DOS or using standard text-mode editors by using the combination keystroke of holding the Alt key and using the Numeric Keypad to enter the decimal value of the symbol.
Page 190: B Ascii Character Set
ASCII Character Set Table B-1. (Continued) ASCII Character Set Symbol Symbol Symbol Symbol × ¶ § × ¦ Ø Æ ¨ < ´ > Ç á ü í ß é ó â ú ä ñ à Ñ å ª µ ç...
Page 191 ASCII Character Set Table B-1. (Continued) ASCII Character Set Symbol Symbol Symbol Symbol æ ± Æ ô ö ò û ÷ ù ÿ ° Ö · Ü · ¢ £ ¥ ² ƒ Blank NOTES: [1] Symbol not displayed. Keystroke Guide: Dec # Keystroke(s) Ctrl 2...
Page 192 ASCII Character Set 361834-001 Technical Reference Guide...
Page 193 Keyboard C.1 Introduction This appendix describes the HP keyboard that is included as standard with the system unit. The keyboard complies with the industry-standard classification of an “enhanced keyboard” and includes a separate cursor control key cluster, twelve “function” keys, and enhanced programmability for additional functions.
Page 194 Keyboard Scroll Caps Lock Lock Lock Matrix Data/ Drivers Keyboard Keyswitch Interface Keyboard Matrix (System Unit) Matrix Processor Receivers Figure C-1. Keystroke Processing Elements, Block Diagram When the system is turned on, the keyboard processor generates a Power-On Reset (POR) signal after a period of 150 ms to 2 seconds.
Page 195 Keyboard C.2.1 PS/2-Type Keyboard Transmissions The PS/2-type keyboard sends two main types of data to the system; commands (or responses to system commands) and keystroke scan codes. Before the keyboard sends data to the system (specifically, to the 8042-type logic within the system), the keyboard verifies the clock and data lines to the system.
Page 196 C.2.3 Keyboard Layouts Figures C-3 through C-8 show the key layouts for keyboards shipped with HPsystems. Actual styling details including location of the HP logo as well as the numbers lock, caps lock, and scroll lock LEDs may vary. C.2.3.1 Standard Enhanced Keyboards Figure C-3.
Page 197 Keyboard C.2.3.2 Windows Enhanced Keyboards 111 112 Figure C-5. U.S. English Windows (101W-Key) Keyboard Key Positions 48 49 111 112 Figure C-6. National Windows (102W-Key) Keyboard Key Positions Technical Reference Guide 361834-001...
Page 198 Keyboard C.2.3.3 Easy Access Keyboard The Easy Access keyboard is a Windows Enhanced-type keyboard that includes special buttons allowing quick internet navigation. The Easy Access Keyboard uses the PS/2-type connection. Btn 1 Btn 2 Btn 3 Btn 4 Btn 5 Btn 6 Btn 7 Btn 8 Main key positions same as Windows Enhanced (Figures C-5 or C-6).
Page 199 Keyboard C.2.4 Keys All keys generate a Make code (when pressed) and a Break code (when released) with the Pause exception of the key (pos. 16), which produces a Make code only. All keys with the Pause exception of the and Easy Access keys are also typematic, although the typematic action Shift, Ctrl, Alt, Num Lock, Scroll Lock, Caps Lock of the...
Page 200 Keyboard —The keys (pos. 93/95) can be used in conjunction with the same keys available for use Ctrl SysRq) with the keys with the exception that position 14 ( is available instead of position 16 Break ). The key can also be used in conjunction with the numeric keypad keys (pos. 55-57, 72-74, and 88-90) to enter the decimal value of an ASCII character code from 1-255.
Page 201 Keyboard C.2.4.4 Easy Access Keystrokes The Easy Access keyboards(Figures C-7) include additional keys (also referred to as buttons) used to streamline internet access and navigation. These buttons, which can be re-programmed to provide other functions, have the default functionality described below: 8-Button Easy Access Keyboard: Button # Description Default Function...
Page 202 Keyboard C.2.5 Keyboard Commands Table C-1 lists the commands that the keyboard can send to the system (specifically, to the 8042-type logic). Table C-1. Keyboard-to-System Commands Command Value Description Key Detection Error/Over/run 00h [1] Indicates to the system that a switch closure couldn’t be identified.
Page 203 Keyboard C.2.6 Scan Codes The scan codes generated by the keyboard processor are determined by the mode the keyboard is operating in. Mode 1: In Mode 1 operation, the keyboard generates scan codes compatible with 8088-/8086-based systems. To enter Mode 1, the scan code translation function of the keyboard controller must be disabled.
Page 204 Keyboard Table C-2. (Continued) Keyboard Scan Codes Make/Break Codes (Hex) Pos. Legend Mode 1 Mode 2 Mode 3 Print Scrn E0 2A E0 37/E0 B7 E0 AA E0 2A E0 7C/E0 F0 7C E0 F0 12 57/na E0 37/E0 B7 [1] [2] E0 7C/E0 F0 7C [1] [2] 54/84 [3] 84/F0 84 [3]...
Page 205 Keyboard Table C-2. (Continued) Keyboard Scan Codes Make/Break Codes (Hex) Pos. Legend Mode 1 Mode 2 Mode 3 Num Lock 45/C5 77/F0 77 76/na E0 35/E0 B5 E0 4A/E0 F0 4A 77/na E0 AA E0 35/E0 B5 E0 2A [1] E0 F0 12 E0 4A/E0 F0 4A E0 12 [1] 37/B7 7C/F0 7C...
Page 206 Keyboard Table C-2. (Continued) Keyboard Scan Codes Make/Break Codes (Hex) Pos. Legend Mode 1 Mode 2 Mode 3 4E/CE [6] 79/F0 79 [6] 7C/F0 7C Caps Lock 3A/BA 58/F0 58 14/F0 14 1E/9E 1C/F0 1C 1C/F0 1C 1F/9F 1B/F0 1B 1B/F0 1B 20/A0 23/F0 23...
Page 207 Keyboard Table C-2. (Continued) Keyboard Scan Codes Make/Break Codes (Hex) Pos. Legend Mode 1 Mode 2 Mode 3 35/B5 4A/F0 4A 4A/F0 4A Shift (right) 36/B6 59/F0 59 59/F0 59 E0 48/E0 C8 E0 75/E0 F0 75 63/F0 63 E0 AA E0 48/E0 C8 E0 2A [4] E0 F0 12 E0 75/E0 F0 75 E0 12 [5] E0 2A E0 48/E0 C8 E0 AA [6] E0 12 E0 75/E0 F0 75 E0 F0 12 [6]...
Page 208 Keyboard Table C-2. (Continued) Keyboard Scan Codes Make/Break Codes (Hex) Pos. Legend Mode 1 Mode 2 Mode 3 (Win95) [7] E0 5B/E0 DB E0 1F/E0 F0 1F 8B/F0 8B E0 AA E0 5B/E0 DB E0 2A [4] E0 F0 12 E0 1F/E0 F0 1F E0 12 [5] E0 2A E0 5B/E0 DB E0 AA [6] E0 12 E0 1F/E0 F0 1F E0 F0 12 [6] (Win95) [7] E0 5C/E0 DC...
Page 209 Keyboard C.3 Connectors Two types of keyboard interfaces may be used in HP/Compaq systems: PS/2-type and USB-type. System units that provide a PS/2 connector will ship with a PS/2-type keyboard but may also support simultaneous connection of a USB keyboard. Systems that do not provide a PS/2 interface will ship with a USB keyboard.
Page 210 Keyboard C-18 361834-001 Technical Reference Guide...
Page 211 Index Numerics 8259 Mode 4-12 I/O map 4-26 IDE (PATA) Connector 4-3 integrated graphics controller (IGC). 6-2 AC97 Audio Controller 5-31 interrupts, hardware 4-11 Advanced Digital Display (ADD2) 6-22 interrupts, PCI 4-13 advanced, Computer Setup heading 7-13 APIC Mode 4-13 audible (beep) indications 4-24 keyboard interface 5-24 audio codec 32...
Page 212 Universal Serial Bus (USB) interface 5-25 upgrading BIOS 8-2 upgrading graphics 6-5 USB 5-25 VGA connector 6-6 Web sites Adobe Systems, Inc. 1-1 HP 1-1 Intel Corporation 1-1 Standard Microsystems Corporation 1-1 USB user group 1-1 Index-2 361834-001 Technical Reference Guide...

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