Power Management - Xilinx DK-V7-VC709-G User Manual

Table 1-20: VITA 57.1 FMC HPC J35 Connections to FPGA U1 (Cont'd)
J35
FMC1 Net Name
HPC Pin
J31 FMC1_HPC_HB11_N
J33 FMC1_HPC_HB15_P
J34 FMC1_HPC_HB15_N
J36 FMC1_HPC_HB18_P
J37 FMC1_HPC_HB18_N
J39 FMC1_VIO_B_M2C
Notes:
1. No I/O standards are associated with MGT connections.
2. FMC1_VIO_B_M2C is sourced by a FMC card which supports the HB bus, when plugged onto the HPC connector J35.
3. FMC1_VIO_B_M2C is a variable voltage but it cannot exceed the fixed VADJ 1.8V value.

Power Management

[Figure
The VC709 board power distribution diagram is shown in
The PCB layout and power system have been designed to meet the recommended criteria
described in 7 Series FPGAs PCB Design and Pin Planning Guide (UG483)
The J5 keyed PMBus connector has three LVCMOS18 connections to the XCVC190T FPGA
U1.
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•
•
VC709 Evaluation Board
UG887 (v1.4) December 4, 2014
I/O XCVX690T
Standard (U1) Pin
LVCMOS18 J22
LVCMOS18 M21
LVCMOS18 L21
LVCMOS18 G21
LVCMOS18 G22
(1) (3)
1-2, callout 26]
J5 pin 9 net PMBUS_CLK is level-shifted to 1.8V by Q8 and is connected to U1 bank 15
pin AW37.
J5 pin 10 net PMBUS_DATA is level-shifted to 1.8V by Q6 and is connected to U1 bank
15 pin AY39.
J5 pin 8 net PMBUS_ALERT is level-shifted to 1.8V by Q7 and is connected to U1 bank
15 pin AV38.
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J35
FMC1 Net Name
HPC Pin
K31 FMC1_HPC_HB10_P
K32 FMC1_HPC_HB10_N
K34 FMC1_HPC_HB14_P
K35 FMC1_HPC_HB14_N
K37 FMC1_HPC_HB17_CC_P
K38 FMC1_HPC_HB17_CC_N
K40 FMC1_VIO_B_M2C
Feature Descriptions
XCVX690T
I/O
Standard
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
Figure 1-25.
[Ref 7].
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(U1)
Pin
M22
L22
J21
H21
M24
L24
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