I2C Bus - Xilinx DK-V7-VC709-G User Manual

I2C Bus

[Figure
The VC709 board implements a single I
IIC_SDA_SCL, pin AT35), which is routed through a TI Semiconductor PCA9548A 1-to-8
channel I
The bus switch I
to select the desired downstream device.
The four SFP+ connectors SFP1 (P3), SFP2 (P2), SFP3 (P4), and SFP4 (P5) are addressed
through a secondary PCA9546A 1-to-4 channel I
bus topology is shown in
X-Ref Target - Figure 1-17
User applications that communicate with devices on one of the downstream I
must first set up a path to the desired bus through the U52 bus switch at I
(0b1110100).
switch U14 is at I²C address 0x75 (0b1110101) and the SFP+ modules all have the same
address 0x50 (0b1010000).
Table 1-17: I
PCA9548
USER_CLK_SDL/SCL
FMC1_HPC_IIC_SDA/SCL
NOT USED
VC709 Evaluation Board
UG887 (v1.4) December 4, 2014
1-2, callout 14, 15]
2
C bus switch (U52). The bus switch can operate at speeds up to 400 kHz.
2
C address is 0x74 (0b01110100) and must be addressed and configured
Figure
U1
FPGA
Bank 15
(2.5V)
IIC_SDA/SCL_MAIN
SFP_IIC_SDA/SCL
Figure 1-17: I
Table 1-17 lists the address for each bus. The secondary (SFP+ access) bus
2
C Bus Addresses
2
I C Bus
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2
C port on the FPGA (IIC_SDA_MAIN, pin AU32;
2
C bus switch (U14). The VC709 board I
1-17.
U52
PCA9548
1 2 C 1-to-8
Bus Switch
CH0 - USER_CLK_SDL/SCL
CH1 - FMC1_HPC_IIC_SDA/SCL
CH2 - Not used
CH3 - EEPROM_IIC_SDA/SCL
CH4 - SFP_IIC_SDA/SCL
CH5 - Not used
CH6 - IIC_SDA/SCL_DDR3
CH7 - SI5324_SDA/SCL
0x74
U14
PCA9546
1 2 C 1-to-4
Bus Switch
CH0 -SFP1_IIC_SDA/SCL
CH1 -SFP2_IIC_SDA/SCL
CH2 -SFP3_IIC_SDA/SCL
CH3 -SFP4_IIC_SDA/SCL
0x75
2
C Bus Topology
2
I C Switch
Position
NA
0b1110100
0
0b1011101
1
0bxxxxx00
2
NOT USED
Feature Descriptions
UG887_c1_16_090612
2
C buses
2
C address 0x74
2
I C Address
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2
C
47