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Chapter 3
Timing Diagrams
PCLK
ACK
REQ
Data Out Valid
Parameter
Input Parameters
t
Setup time from REQ valid to PCLK
rs
t
Hold time from PCLK to REQ invalid
rh
Output Parameters
t
PCLK cycle time
pc
t
PCLK high pulse duration
pw
t
PCLK to ACK valid
pa
t
Hold time from PCLK to ACK invalid
ah
t
PCLK to output data valid
pdo
t
Hold time from PCLK to output data
doh
invalid
t
Setup time from input data valid to PCLK
dis
t
Hold time from PCLK to input data invalid
dih
1
t
= programmable delay from 100 to 700 ns, or 50 ns if programmable delay is 0. Timebase stability for the onboard
pc
20 MHz clock source is 50 ppm.
All timing values are in nanoseconds.
NI 653X User Manual
t
pw
t
pa
t
pdo
Description
Figure 3-8. Burst Output Timing Diagram (PCLK Reversed)
t
pc
t
rs
3-10
t
ah
t
rh
t
doh
Minimum
Maximum
12
0
50
700
t
/2 – 5
t
pc
pc
—
3
—
4
0
0
—
—
1
/2 + 5
18
—
28
—
—
—
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