Sony DSR-1 Service Manual page 137

12 66
A0 NT4F
13 67 INPUT
A1 PL4F
14 68 A0-A5
A2 PL8F
16 69 ALCK
A3 PM8F
17 BKIN
A4
18 99 BKUP
A5 D0
9 100 CK1I
CS D1
10 1 CSHD
WR D2
11 2 CSVD
RD D3
5 CTLI
D4
42 6 DEMI
CSHD D5
43 7 DLYI
CSVD D6
8 DMCK
D7
FRMI
71 30 FWD
LRRV RSYC
27 31 HDI
FWD LREV
26 32 INTE
CTLI DCLK
24 33 K16I
PBTC DATA
25 34
LTCI BER
20 LRRV
X1TC
19 LTCI
X1BE
72 21 LSHI
XINIT REC
73 22 NORM
XRES OUT
74 23 TEST1-TEST9,
BKUP READ
87 TEST11
ALCK
38 PBTC
XBK
37 45 RD
K16I HDO
44 46 REF
HDI VDO
49 47 VCI1
DLYI IFRM
51 48 VCI2
FRMI FRAM
52 50 X1TC
LSHI DLYO
57 55 XRES
VCI1 LSHO
58 56 WR
VCI2 VCEO
61 59
REF LTCO
60 OUTPUT
CFNG
35 BER
DMCK
36 76 BKO
DEMI INTG
39 77 CFNG
BKIN INTL
89 80 CK1O
CK1I INTC
93 81 CK2M
INTE INTR
83 82 CS
TEST1 INTX
84 D0-D7
TEST2
85 88 DATA
TEST3 CK2M
86 41 DCCK
TEST4 BKO
94 91 DCLK
TEST5 CK1O
95 92 DLYO
TEST6 DCCK
96 75 FRAM
TEST7 INTM
97 62 HDO
TEST8 XOUT
98 63 IFRM
TEST9 PORT
64 72 INTC
NORM XINT
70 INTG
TEST11
INTL
INTM
INTR
INTX
LREV
LSHO
LTCO
NT4F,PL4F,
PL8F,PM8F
OUT
PORT
READ
REC
RSYC
VCEO
VDO
X1BE
XBK
XINT
XOUT
DSR-1/1P/V2
;ADDRESS BUS IN
;ARITHMETIC LOGIC UNIT CLOCK IN
;BACKUP IN (NEGATIVE LOGIC)
;BACKUP EXECUTION IN (NEGATIVE LOGIC)
;SYSTEM CLOCK IN
;COMPOSITE SYNC/HD IN
;COMPOSITE SYNC/VD IN
;CTL SIGNAL IN
;LONGITUDINAL TIME AND CONTROL CODE IN
;INPUT TO DELAY CIRCUIT
;LTC DEMODULATE CLOCK IN
;FRAME SIGNAL IN
;CTL DIRECTION SIGNAL IN
;HORIZONTAL SYNC INPUT
;EXTERNAL INTERRUPT IN (POSITIVE LOGIC)
;16KHz CLOCK IN
BACKUP CLOCK IN
;DIRECTION INPUT FOR LTC READER CALCULATION
;GENERATED LTC IN
;LTC SYNCHRINOUS H INPUT
;NORMAL/BACKUP MODE SELECT
;TEST IN
;PLAYBACK LTC IN
;READ IN (NEGATIVE LOGIC)
;REFERENCE OF LTC GENERATOR
;LTC CLOCK IN-1
;EXTERNAL LTC IN
;LTC CLOCK IN-2
;SYSTEM RESET IN (NEGATIVE LOGIC)
;WRITE IN (NEGATIVE LOGIC)
;BI-PHASE MARK ERROR(BIT ERROR)
;BACKUP CONTROL OUT-2 (POSITIVE LOGIC)
;COLOR FRAME ERROR FLAG OUT
;SYSTEM CLOCK OUT
;CLOCK 2M OUT
;CHIP SELECT IN (NEGATIVE LOGIC)
;DATA BUS
;DEMODULATED SERIAL DATA OUT
;LTC DECODE CLOCK OUT
;DEMODULATED CLOCK OUT
;OUTPUT FROM DELAY CIRCUIT
;FRAME SIGNAL OUT -2
;HORIZONTAL SYNC DRIVE OUT
;FRAME SIGNAL OUT -1
;CTL INTERRUPT OUT (POSITIVE LOGIC)
;GENERATOR INTERRUPT OUT (POSITIVE LOGIC)
(POSITIVE LOGIC)
;READER INTERRUPT -1 OUT
;INTERRUPT MIX OUT (POSITIVE LOGIC)
;READER INTERRUPT -2 OUT (POSITIVE LOGIC)
;EXTERNAL LTC INTERRUPT OUT (POSITIVE LOGIC)
;READ REV/FWD BIT OUT
;LTC SYNCHRONOUS SIGNAL H OUT
;LTC SIGNAL OUT
;DEMODULATED COLOR FRAME OUT
;EXTERNAL OUTPUT LTC OUT
;PORT
;READ LTC OUT
;RECORD LTC OUT
;READ SYNC WORD DATA OUT
;LTC CLOCK OUT
;VERTICAL SYNC DRIVE OUT
;BI-PHASE MARK ERROR(NORMAL SPEED READER)
;BACKUP CONTROL OUT-1 (NEGATIVE LOGIC)
;INVERTED INTERRUPT MIX OUT (NEGATIVE LOGIC)
;INVERTED EXTERNAL OUTPUT LTC OUT
HM51W4400BLTT-7 (HITACHI)
C-MOS 1M×4-BIT DYNAMIC RAM
-TOP VIEW-
I/O1 1 GND 20
I/O
I/O2 2 19 I/O4
I/O I/O
WE 3 18 I/O3
IN I/O
RAS 4 17 CAS
IN IN
A9 5 16 OE
IN IN
A0 6 15 A8
IN IN
A1 7 14 A7
IN IN
A2 8 13 A6
IN IN
A3 9 12 A5
IN IN
10 V 11 A4
DD ( +3.3V ) IN
INPUT
A0-A9
A0-A9
CAS
IO1-IO4
RAS
OE
WE
RAS CAS WE
4 17 3
RAS CONTROL CAS CONTROL WE CONTROL
CIRCUIT CIRCUIT CIRCUIT
I/O1 BUFFER I/O2 BUFFER
ROW DECODER & PERIPHERAL CIRCUIT
ROW ADDRESS BUFFER
ADDRESS
6
A0
7
A1
8 1
A2 I/O1
9 2
A3 I/O2
11 18
A4 I/O3
12 19
A5 I/O4
13
A6
14
A7
15
A8
17
CAS
4
RAS
16
OE
3
WE
; ADDRESS INPUTS
; REFRESH ADDRESS INPUTS
; COLUMN ADDRESS STROBE INPUT
; DATA INPUTS/OUTPUTS
; ROW ADDRESS STROBE INPUT
; OUTPUT ENABLE INPUT
; READ/WRITE ENABLE INPUT
OE I/O1 I/O2 I/O3 I/O4
16 1 2 18 19
OE CONTROL
CIRCUIT
I/O3 BUFFER I/O4 BUFFER
COLUMN ADDRESS BUFFER
6-9, 11-15
A0-A9
14-23
IC