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IC
CXD2193AR-ER (SONY)
C-MOS AFC FOR SYNC SIGNAL
–TOP VIEW–
49
GND
50
51
52
53
54
V
DD(+3V)
55
56
57
GND
58
V
DD(+3V)
59
60
61
62
63
64
7
C-VID
3
S-VID
61
C-SM
34
CAM-FR
35
PB FR
54
TEN
23
CK
52
PAL
30
RST
36
CAM-H
37
PB-H
38
AFC-REF
19
TEST5
18
PHASE
20
AFC
14-16
7
C-VID
4
CMP
6
FCL
32
3
S-VID
31
30
1
SLICE
29
2
SYNC-TIP
28
61
CSM
27
34
CAM-FR
V
26
DD(+3V)
35
FB-FR
GND
25
54
TEN
24
23
CK
23
52
PAL
22
30
RST
21
36
20
CAM-H
37
19
PB-H
18
18
PHASE
GND
17
20
AFC
16
HOLD
8
OP1
13
VCO1
47
TEST0
45
TEST1
44
TEST2
40
TEST3
39
TEST4
19
TEST5
29
CLR
50
XXA
51
IR1
32
EXT
31
CAM
64
VAS
4
6
62
63
1
FEEDBACK CLAMP
H-NOISE
SYNC SEP
REJECT
SYNC
SEP
V
DET
O/E
DET
O/E, V
DET
O/E, V
DET
V & H
PULSE
GEN
MALF-H
KILLER
EDGE
DTECTOR
64 31 32 51 50 29 39 40 44 45 47
INPUT
60
C-SYNC
AFC
; AFC LOCK PHASE ADJUSTMENT INPUT
62
SYNCO
CAM
; CAMERA/LINE SELECT INPUT (H = CAMERA, L = LINE)
63
CPO
CAM-FR
; FRAME SIGNAL IN CAMERA INPUT MODE
CAM-H
; H SYNC INPUT IN CAMERA INPUT MODE
CK
; MASTER CLOCK INPUT (6.75MHz)
CLR
; DIRECT CLEAR INPUT
CMP
; SLICE LEVEL OF THE FEEDBACK CLAMP SYSTEM
53
RES
CSM
; ABNORMAL SIGNAL COMPENSATOR ON/OFF (H = ON, L = OFF)
55
FL-DT
C-VID
; VIDEO INPUT OF THE FEEDBACK CLAMP SYSTEM
22
VD
EXT
; EXTERNAL/INTERNAL SELECT INPUT (H = EXT, L = INT)
46
LVD
FB-FR
; FRAME SIGNAL IN NORMAL PB MODE
28
AFC-HD
FCL
; SYNC-TIP LEVEL OF THE FEEDBACK CLAMP SYSTEM
21
AFC-DIR
HOLD
; AFC ERROR HOLD INPUT (L = ERROR HOLD)
OP1
; OPERATIONAL AMPLIFIER INPUT
PAL
; SYSTEM SELECT INPUT (H = PAL, L = NTSC)
38
AFC-REF
PB-H
; H SYNC INPUT IN NORMAL PB MODE
PHASE
; AFC PHASE ADJUST INPUT
12
ERROR1
RST
; AFC RESET INPUT (L = RESET)
11
ERROR2
S-VID
; VIDEO INPUT OF THE SYNC CLAMP SYSTEM
9
OP2
SLICE
; SLICE LEVEL OF THE SYNC CLAMP SYSTEM
14
VCO2
SYNC-TIP
; SYNC-TIP LEVEL OF THE SYNC CLAMP SYSTEM
15
13.5MHz
TEN
; V SYNC ADJUST INPUT
24
6.75CK
VAS
; V SYNC ADJUST INPUT
27
6.75CK
VCO1
; VCO INPUT
41
SPCK0
43
SPCK1
OUTPUT
48
SPCK2
13.5MHz
; 13.5MHz OUTPUT
56
SPCK3
6.75CK
; 6.75MHz OUTPUT
59
SPCK4
AFC-HD
; HD FROM THE AFC OUTPUT
AFC-REF
; AFC REFERENCE OUTPUT
C-SYNC
; SEPARATED SYNC OUTPUT OF THE SYNC CLAMP SYSTEM
ERROR1
; AFC MAIN LOOP PHASE ERROR OUTPUT
ERROR2
; AFC SUB LOOP PHASE ERROR OUTPUT
FL-DT
; ODD/EVEN DETECTED OUTPUT (H = 1st and 3rd FIELDS)
LVD
; VERTICAL SYNC OUTPUT (FOR NO SIGNAL DETECTION)
OP2
; OPERATIONAL AMPLIFIER OUTPUT
RES
; V SYNC LPF OUTPUT (FOR TEST)
SPCK1 - SPCK4
; 13.5MHz OUTPUT
SYNCO
; SEPARATED SYNC OUTPUT (FOR TEST)
VCO2
; VCO OUTPUT
VD
; DETECTED VERTICAL SYNC OUTPUT
INPUT/OUTPUT
AFC-DIR
; AFC DIRECT (FOR TEST)
CPO
; SYNC CLAMP MONITORING TERMINAL
IR1
; FOR TEST
XXA
; FOR TEST
2
DELAY
LINE
H COUNTER
2/868 (NTSC)
2/864 (PAL)
ERROR
SKEW
DET
PHASE
H-EDGE
DET
H-WIDTH
16
12 11
8
60
C-SYNC
53
RES
55
FL-DET
22
VD
46
LVD
28
AFC-HD
21
AFC-DIR
24
6.75CK
2
27
6.75CK
41
SPCK0
43
SPCK1
48
SPCK2
56
SPCK3
OPE
59
VCO
SPCK4
AMP
9 13
14 15
DSR-1/1P/V2
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