Marantz SR8001 Service Manual page 133

IC63 : CD0040AF
1
No. Name I/O Attr ibut e
1 OVDD P -
2 CLKI In CMOS
3 TEST7 In CMOS
4 PLL_EN In CMOS
5 PI0 In CMOS
6 PI1 In CMOS
7 PI2 In CMOS
8 PI3 In CMOS
9 PI4 In CMOS
10 PI5 In CMOS
11 PI6 In CMOS
12 PI7 In CMOS
13 PI8 In CMOS
14 PI9 In CMOS
15 NHSI In Schmitt
16 NVSI In Schmitt
17 OVSS P -
18 THMD In Schmitt
19 CVSS P -
20 NVSO Out 2mA
21 NHSO Out 2mA
22 PO9 Inout CMOS / 2mA
23 PO8 Inout CMOS / 2mA
24 PO7 Inout CMOS / 2mA
25 PO6 Inout CMOS / 2mA
26 OVDD P -
27 OVSS P -
28 PO5 Inout CMOS / 2mA
29 PO4 Inout CMOS / 2mA
30 PO3 Inout CMOS / 2mA
31 PO2 Inout CMOS / 2mA
32 PO1 Inout CMOS / 2mA
33 PO0 Inout CMOS / 2mA
34 TEST0 In CMOS
35 OVSS P -
36 OVDD P -
37 CVDD P -
38 TEST1 In CMOS
39 TEST2 In CMOS
40 CLKO Out 2mA
41 YO9 Out 4mA
42 YO8 Out 4mA
43 YO7 Out 4mA
44 YO6 Out 4mA
45 YO5 Out 4mA
46 OVDD P -
47 OVSS P -
48 YO4 Out 4mA
49 YO3 Out 4mA
50 YO2 Out 4mA
51 YO1 Out 4mA
52 YO0 Out 4mA
53 OVDD P -
54 CVSS P -
55 OVSS P -
56 CO0 Out 4mA
57 CO1 Out 4mA
58 CO2 Out 4mA
59 CO3 Out 4mA
60 CO4 Out 4mA
61 OVDD P -
62 OVSS P -
63 CO5 Out 4mA
64 CO6 Out 4mA
65 CO7 Out 4mA
66 CO8 Out 4mA
67 CO9 Out 4mA
68 FILM Out 2mA
69 RFFI In CMOS
Functional Description
Positive supply voltage(+3.3V) for Pad Ring
System Clock Input (27MHz)
Test purpose only(must be connected to Ground)
PLL enable
ITU-R BT.656/601 Input (LSB)
ITU-R BT.656/601 Input
ITU-R BT.656/601 Input
ITU-R BT.656/601 Input
ITU-R BT.656/601 Input
ITU-R BT.656/601 Input
ITU-R BT.656/601 Input
ITU-R BT.656/601 Input
ITU-R BT.656/601 Input
ITU-R BT.656/601 Input (MSB)
Active low horizontal sync input
Active low vertical sync input
Digital ground for Pad Ring
Through mode setting terminal. Usually, this must be
connected to ground.
Digital ground for Core
Active low vertical sync output (Interlace or Progressive)
Refer "11.2Video Output"
Active low horizontal sync output(Interlace or Progressive)
Refer "11.2Video Output"
ITU-R BT.656/601 output (MSB) / clamp signal output / ITU-R
BT. 601 Cb Cr input(MSB)
ITU-R BT.656/601 output / Video active signal output / ITU-R
BT. 601 CbCr input. Refer "11.1Video Input""11.2Video
Output""11.3Through Mode"
ITU-R BT.656/601 output / Video blanking signal output /
ITU-R BT. 601 CbCr input
Refer "11.1Video Input""11.2Video Output"
ITU-R BT.656/601 output / ITU-R BT.601 CbCr input
Refer "11.1Video Input""11.2Video Output"11.3Through
Mode"
Positive supply voltage (+3.3V) for Pad Ring
Digital ground for Pad Ring
ITU-R BT.656/601 output / ITU-R BT.601 CbCr input
Refer "11.1Video Input""11.2Video Output""11.3Through
Mode"
ITU-R BT.656/601 output / ITU-R BT.601 CbCr input
Refer "11.1Video Input""11.2Video Output""11.3Through
Mode"
ITU-R BT.656/601 output / ITU-R BT.601 CbCr input
Refer "11.1Video Input""11.2Video Output""11.3Through
Mode"
ITU-R BT.656/601 output / ITU-R BT.601 CbCr input
Refer "11.1Video Input""11.2Video Output""11.3Through
Mode"
ITU-R BT.656/601 output / ITU-R BT.601 CbCr input
Refer "11.1Video Input""11.2Video Output""11.3Through
Mode"
ITU-R BT.656/601 output (LSB) / ITU-R BT.601 CbCr input
Refer "11.1Video Input""11.2Video Output""11.3Through
Mode"
Test purpose only (must be connected to ground)
Digital ground for Pad Ring
Positive supply voltage (+3.3V) for Pad Ring
Digital positive supply voltage (+2.5V) for core
Test purpose only (must be connected to ground)
Test purpose only (must be connected to ground)
Clock output(27MHz)
ANSI/SMPTE 293M Y output(MSB)
ANSI/SMPTE 293M Y output
ANSI/SMPTE 293M Y output
ANSI/SMPTE 293M Y output
ANSI/SMPTE 293M Y output
Positive supply voltage (+3.3V) for Pad Ring
Digital ground for Pad Ring
ANSI/SMPTE 293M Y output
ANSI/SMPTE 293M Y output
ANSI/SMPTE 293M Y output
ANSI/SMPTE 293M Y output
ANSI/SMPTE 293M Y output (LSB)
Positive supply voltage (+3.3V) for Pad Ring
Digital ground for core
Digital ground for Pad Ring
ANSI/SMPTE 293M Cb/Cr output
ANSI/SMPTE 293M Cb/Cr output
ANSI/SMPTE 293M Cb/Cr output
ANSI/SMPTE 293M Cb/Cr output
ANSI/SMPTE 293M Cb/Cr output
Positive supply voltage (+3.3V) for Pad Ring
Digital ground for Pad Ring
ANSI/SMPTE 293M Cb/Cr output
ANSI/SMPTE 293M Cb/Cr output
ANSI/SMPTE 293M Cb/Cr output
ANSI/SMPTE 293M Cb/Cr output
ANSI/SMPTE 293M Cb/Cr output (MSB)
Film sequence detection flag output. Refer "11.4.1.9Film
detection Flag Output"
MPEG flag (Repeat First Field) input port. Refer"11.4.1.6Film
I/P Conversion""11.4.1.8Film Sequence Flag Control Mode"
1
No. Name I/O Attr ibut e
70 OVSS P
71 CVDD P
72 IVDD P
73 OVDD P
74 MD19 Inout CMOS, pull-up /
CMOS, pull-up /
75 MD18 Inout
76 MD17 Inout CMOS, pull-up /
77 MD16 Inout CMOS, pull-up /
78 OVDD P
79 OVSS P
80 MA3 Out
81 MA4 Out
82 MA2 Out
83 MA5 Out
84 OVDD P
85 OVSS P
86 MA1 Out
87 MA6 Out
88 MA0 Out
89 MA7 Out
90 OVSS P
91 IVSS P
92 CVSS P
93 OVDD P
94 MA10 Out
95 MA8 Out
96 MA11 Out
97 MA9 Out
98 OVDD P
99 OVSS P
100 RAS Out
101 DQM Out
102 CAS Out
103 MCLK Out
104 WE Out
105 TEST3 In
106 TEST4 In
107 OVSS P
108 OVDD P
109 CVDD P
110 MD7 Inout CMOS, pull-up /
111 MD8 Inout CMOS, pull-up /
* 2
112 MD6 Inout CMOS, pull-up /
* 2
113 MD9 Inout CMOS, pull-up /
114 OVDD P
115 OVSS P
116 MD5 Inout CMOS, pull-up /
117 MD10 Inout CMOS, pull-up /
118 MD4 Inout CMOS, pull-up /
119 MD11 Inout CMOS, pull-up /
120 OVDD P
121 OVSS P
CMOS, pull-up /
122 MD3 Inout
123 MD12 Inout CMOS, pull-up /
124 MD2 Inout CMOS, pull-up /
125 MD13 Inout CMOS, pull-up /
126 OVSS P
127 CVSS P
128 OVDD P
129 MD1 Inout CMOS, pull-up /
130 MD14 Inout CMOS, pull-up /
131 MD0 Inout CMOS, pull-up /
132 MD15 Inout CMOS, pull-up /
133 SLV In
134 RFFO Out
135 SDA Inout Schmitt, 3.3V /
136 SCL In Schmitt, 3.3V
137 SRN In
138 OVSS P
139 CVDD P
140 PLL_VDD P
141 VPDX In
142 TEST6 In
143 PLL_GN P
D
144 IVDD P
Note: *1 P10 and P11 should be connected to GND at the time of 8bit input.
*2 PO0 and PO1 should connected to GND at the time of 8bit input.
*3 Although the same bidirectional buffer as PO is used in order to unite PO and timing at the time of PO
input, it is always fixed as an input.
*4 The initial-setting value or the initial state in a reset period and after reset release.
167
Functional Description
- Digital ground for Pad Ring
- Digital positive supply voltage (+2.5V) for core
- Positive supply voltage (+3.3V) for Pad Ring
- Positive supply voltage (+3.3V) for Pad Ring
Data input/output port for SDRAM
4mA
Data input/output port for SDRAM
4mA
Data input/output port for SDRAM
4mA
Data input/output port for SDRAM
4mA
- Positive supply voltage (+3.3V) for Pad Ring
- Digital ground for Pad Ring
4mA Address output port for SDRAM
4mA Address output port for SDRAM
4mA Address output port for SDRAM
4mA Address output port for SDRAM
- Positive supply voltage (+3.3V) for Pad Ring
- Digital ground for Pad Ring
4mA Address output port for SDRAM
4mA Address output port for SDRAM
4mA Address output port for SDRAM (LSB)
4mA Address output port for SDRAM
- Digital ground for Pad Ring
- Digital ground for Pad Ring
- Digital ground for Pad Ring for Core
- Positive supply voltage (+3.3V) for Pad Ring
4mA Address output port for SDRAM
4mA Address output port for SDRAM
4mA Address output port for SDRAM (MSB)
4mA Address output port for SDRAM
- Positive supply voltage (+3.3V) for Pad Ring
- Digital ground for Pad Ring
4mA Row Address Strobe command output port for SDRAM
4mA DQM output port for SDRAM. In addition, please connect the
CKE terminal of SDRAM to the power supply of SDRAM
4mA Column Address Strobe command output port for SDRAM
4mA Clock output port for SDRAM (54MHz)
4mA Write Enable output port for SDRAM
CMOS Test purpose only (must be connected to ground)
CMOS Test purpose only (must be connected to ground)
- Digital ground for Pad Ring
- Positive supply voltage (+3.3V) for Pad Ring
- Digital positive supply voltage (+2.5V) for core
Data input/output port for SDRAM
4mA
Data input/output port for SDRAM
4mA
Data input/output port for SDRAM
4mA
Data input/output port for SDRAM
4mA
- Positive supply voltage (+3.3V) for Pad Ring
- Digital ground for Pad Ring
Data input/output port for SDRAM
4mA
Data input/output port for SDRAM
4mA
Data input/output port for SDRAM
4mA
Data input/output port for SDRAM
4mA
- Positive supply voltage (+3.3V) for Pad Ring
-
Digital ground for Pad Ring
Data input/output port for SDRAM
4mA
Data input/output port for SDRAM
4mA
Data input/output port for SDRAM
4mA
Data input/output port for SDRAM
4mA
- Digital ground for Pad Ring
- Digital ground for core
- Positive supply voltage (+3.3V) for Pad Ring
Data input/output port for SDRAM
4mA
Data input/output port for SDRAM
4mA
Data input/output port for SDRAM
4mA
Data input/output port for SDRAM
4mA
CMOS Slave address selection input for I2C. Slave address is set up
to 0x72 when SLV is "0", 0x70 when "1".
2mA MPEG flag (Repeat First Field) output port. If not used, leave
open.
Data input/output of MPU interface
4mA
Clock input of MPU interface
Schmitt System reset input(negative)
- Digital ground for Pad Ring
- Digital positive supply voltage (+2.5V) for core
- Digital positive supply voltage (+2.5V) for PLL
CMOS Must be connected to ground
CMOS Test purpose only (must be connected to ground)
- Ground for PLL
- Positive supply voltage (+3.3V) for Pad Ring