Motorola PowerQUICC II MPC8280 Series Reference Manual page 274

Signal Descriptions
7.2.1.3.2 Address Bus Busy (ABB)—Input
Following are the state meaning and timing comments for the ABB input signal.
State Meaning
Timing Comments Assertion—May occur whenever the MPC8280 must be prevented
7.2.2 Address Transfer Start Signal
In the internal only mode the address transfer start signal has no meaning.
Address transfer start signal are input and output signals that indicate that an address bus
transfer has begun.
7.2.2.1 Transfer Start (TS)
The TS signal is both an input and an output signal on the MPC8280.
7.2.2.1.1 Transfer Start (TS)—Output
Following are the state meaning and timing comments for the TS output signal.
State Meaning
Timing Comments Assertion/Negation—Driven and asserted on the cycle after a
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Turn-Off Sequencing—Negates for a fraction of a bus cycle (1/2
minimum, depends on clock mode) starting the cycle following the
assertion of AACK. It then goes to the high impedance state.
Asserted—Indicates that external device is the address bus master.
Negated—Indicates that the address bus may be available for use by
the MPC8280 (see BG). The MPC8280 also tracks the state of ABB
on the bus from the TS and AACK inputs. (See section on address
arbitration phase.)
from using the address bus.
Negation—May occur whenever the MPC8280 may use the address
bus.
Asserted—Indicates that the MPC8280 has started a bus transaction
and that the address bus and transfer attribute signals are valid. It is
also an implied data bus request if the transfer attributes TT[0–4]
indicate that a data tenure is required for the transaction.
Negated—Has no special meaning during a normal transaction.
qualified BG is accepted by MPC8280; remains asserted for one
clock only. Negated for the remainder of the address tenure.
Assertion is coincident with the first clock that ABB is asserted.
High Impedance—Occurs the cycle following the assertion of
AACK (same cycle as ABB negation).
MPC8280 PowerQUICC II Family Reference Manual
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