Motorola PowerQUICC II MPC8280 Series Reference Manual page 171

Table 3-1. Internal Memory Map (continued)
Address
(offset)
0x11A18– Reserved
0x11A1F
0x11A20 SCC2 general mode register (low) (GSMR_L2)
0x11A24 SCC2 general mode register (high) (GSMR_H2)
0x11A28 SCC2 protocol-specific mode register (PSMR2)
0x11A2A Reserved
0x11A2C SCC2 transmit-on-demand register (TODR2)
0x11A2E SCC2 data synchronization register (DSR2)
0x11A30 SCC2 event register (SCCE2)
0x11A34 SCC2 mask register (SCCM2)
0x11A36 Reserved
0x11A37 SCC2 status register (SCCS2)
0x11A38– Reserved
0x11A3F
0x11A40 SCC3 general mode register (GSMR_L3)
0x11A44 SCC3 general mode register (GSMR_H3)
MOTOROLA
Freescale Semiconductor, Inc.
Register
SCC2
SCC3
Chapter 3. Memory Map
For More Information On This Product,
Go to: www.freescale.com
R/W Size Reset
— 8 bytes —
R/W 32 bits 0x0000_0000 20.1.1/-3
R/W 32 bits 0x0000_0000
R/W 16 bits 0x0000
— 16 bits —
R/W 16 bits 0x0000
R/W 16 bits 0x7E7E
R/W 16 bits 0x0000
R/W 16 bits 0x0000
— 8 bits —
R/W 8 bits 0x00
— 8 bytes —
R/W 32 bits 0x0000_0000 20.1.1/-3
R/W 32 bits 0x0000_0000
Section/Page
—
20.1.2/-9
21.16/-14
(UART)
22.8/-7 (HDLC)
23.11/-10
(BISYNC)
24.9/-9
(Transparent)
25.17/-15
(Ethernet)
—
20.1.4/-10
20.1.3/-9
21.19/-20
(UART)
22.11/-13
(HDLC)
23.14/-15
(BISYNC)
24.12/-12
(Transparent)
25.20/-21
(Ethernet)
—
21.20/-22
(UART)
22.12/-15
(HDLC)
23.15/-16
(BISYNC)
24.13/-13
(Transparent)
—
3-19