Clg Osc3 Control Register - Epson S1C31W65 Technical Manual

2 POWER SUPPLY, RESET, AND CLOCKS
Table 2.6.7 Setting Oscillation Inverter Gain at OSC1 Boost Startup
Note: The CLGOSC1.INV1B[1:0] bits must be set to a value equal to or larger than the CLGOSC1.
INV1N[1:0] bits.
Bits 5–4 INV1N[1:0]
These bits set the oscillation inverter gain applied at normal operation of the OSC1 oscillator circuit.
Table 2.6.8 Setting Oscillation Inverter Gain at OSC1 Normal Operation
Bits 3–2 Reserved
Bits 1–0 OSC1WT[1:0]
These bits set the oscillation stabilization waiting time for the OSC1 oscillator circuit.

CLG OSC3 Control Register

Register name Bit
CLGOSC3 15–13 –
12–10 OSC3FQ[2:0]
9
8
7–6 –
5–4 OSC3INV[1:0]
3
2–0 OSC3WT[2:0]
Bits 15–13 Reserved
Bits 12–10 OSC3FQ[2:0]
These bits set the OSC3CLK frequency when internal oscillator is selected as the OSC3 oscillator
type.
Table 2.6.10 OSC3CLK Frequency Setting (OSC3 Internal Oscillator)
Bit 9 OSC3MD
This bit selects an oscillator type of the OSC3 oscillator circuit.
1 (R/WP): Crystal/ceramic oscillator
0 (R/WP): Internal oscillator
Bits 8–6 Reserved
2-24
CLGOSC1.INV1B[1:0] bits
0x3
0x2
0x1
0x0
CLGOSC1.INV1N[1:0] bits
0x3
0x2
0x1
0x0
Table 2.6.9 OSC1 Oscillation Stabilization Waiting Time Setting
CLGOSC1.OSC1WT[1:0] bits
0x3
0x2
0x1
0x0
Bit name Initial
0x0
0x5
OSC3MD
–
0x0
0x3
–
0x6
CLGOSC3.OSC3FQ[2:0] bits
0x7
0x6
0x5
0x4
0x3–0x0
Seiko Epson Corporation
Inverter gain
Max.
↑
↓
Min.
Inverter gain
Max.
↑
↓
Min.
Oscillation stabilization waiting time
65,536 clocks
16,384 clocks
4,096 clocks
Reserved
Reset R/W
– R –
H0 R/WP
0 H0 R/WP
0 – R
– R
H0 R/WP
0 – R
H0 R/WP
OSC3CLK frequency
32 MHz
24 MHz
16 MHz
12 MHz
8 MHz
Remarks
S1C31W65 TECHNICAL MANUAL
(Rev. 1.1)