Clg Osc3 Control Register - Epson S1C17W18 Technical Manual

2 POWER SUPPLY, RESET, AND CLOCKS

CLG OSC3 Control Register

Register name Bit
CLGOSC3 15–13 –
12–10 OSC3FQ[2:0]
9–8 OSC3MD[1:0]
7–6 –
5–4 OSC3INV[1:0]
3
2–0 OSC3WT[2:0]
Bits 15–13 Reserved
Bits 12–10 OSC3FQ[2:0]
These bits set the oscillation frequency when the internal oscillator is selected as the OSC3 oscillator.
Bits 9–8 OSC3MD[1:0]
These bits select an oscillator type of the OSC3 oscillator circuit.
Bits 7–6 Reserved
Bits 5–4 OSC3INV[1:0]
These bits set the oscillation inverter gain when crystal/ceramic oscillator is selected as the OSC3 os-
cillator type.
Bit 3 Reserved
Bits 2–0 OSC3WT[2:0]
These bits set the oscillation stabilization waiting time for the OSC3 oscillator circuit.
Table 2.6.12 OSC3 Oscillation Stabilization Waiting Time Setting
2-22
Bit name Initial
0x0
0x3
0x0
0x0
0x1
–
0x6
Table 2.6.9 OSC3 Internal Oscillator Frequency Setting
CLGOSC3.OSC3FQ[2:0] bits
0x7–0x6
0x5
0x4
0x3
0x2
0x1
0x0
Table 2.6.10 OSC3 Oscillator Type Selection
CLGOSC3.OSC3MD[1:0] bits
0x3
0x2
0x1
0x0
Table 2.6.11 OSC3 Oscillation Inverter Gain Setting
CLGOSC3.OSC3INV[1:0] bits
0x3
0x2
0x1
0x0
CLGOSC3.OSC3WT[2:0] bits
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
Seiko Epson Corporation
Reset R/W
– R –
H0 R/WP
H0 R/WP
– R
H0 R/WP
0 – R
H0 R/WP
OSC3 internal oscillator frequency
Reserved
250 kHz
384 kHz
4 MHz
2 MHz
1 MHz
500 kHz
OSC3 oscillator type
Reserved
Crystal/ceramic oscillator
CR oscillator
Internal oscillator
Inverter gain
Max.
↑
↓
Min.
Oscillation stabilization waiting time
65,536 clocks
16,384 clocks
4,096 clocks
1,024 clocks
256 clocks
64 clocks
16 clocks
4 clocks
Remarks
S1C17W18 TECHNICAL MANUAL
(Rev. 1.2)