Vector Table Offset Address (Vtor); Priority Of Interrupts; Peripheral Circuit Interrupt Control; Nmi - Epson S1C31W65 Technical Manual

Interrupt IRQ
Vector address Hardware interrupt name
number number
38 22 VTOR + 0x98
39 23 VTOR + 0x9c
40 24 VTOR + 0xa0
41 25 VTOR + 0xa4
42 26 VTOR + 0xa8
43 27 VTOR + 0xac
44–47 –
*1 Either reset or NMI can be selected as the watchdog timer interrupt via software.

5.2.1 Vector Table Offset Address (VTOR)

The Cortex -M0+ Vector Table Offset Register (VTOR) is provided to set the offset (start) address of the vector
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table in which interrupt vectors are programmed. "VTOR" described in Table 5.2.1 means the value set to this reg-
ister. After an initial reset, VTOR is set to address 0x0. Therefore, even when the vector table location is changed,
it is necessary that at least the reset vector be written to this address. For more information on VTOR, refer to the
documents introduced in Section 3.4, such as "Cortex

5.2.2 Priority of Interrupts

The priorities of SVCall, PendSV, and SysTick are configurable to the desired levels using the Cortex
tem Handler Priority Registers (SHPR2 and SHPR3). The priorities of the interrupt number 16 or later are con-
figurable to the desired levels using the Cortex
value can be set within a range of 0 to 192 (a lower value has a higher priority). The priorities of reset, NMI, and
HardFault are fixed at the predefined values. For more information, refer to the documents introduced in Section 3.4,
such as "Cortex -M0+ Devices Generic User Guide."
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5.3 Peripheral Circuit Interrupt Control

The peripheral circuit that generates interrupts includes an interrupt enable bit and an interrupt flag for each inter-
rupt cause.
Interrupt flag: The flag is set to 1 when the interrupt cause occurs. The clear condition depends on the
peripheral circuit.
Interrupt enable bit: By setting this bit to 1 (interrupt enabled), an interrupt request will be sent to the CPU when
the interrupt flag is set to 1. When this bit is set to 0 (interrupt disabled), no interrupt request
will be sent to the CPU even if the interrupt flag is set to 1. An interrupt request is also sent to
the CPU if the status is changed to interrupt enabled when the interrupt flag is 1.
For specific information on causes of interrupts, interrupt flags, and interrupt enable bits, refer to the respective
peripheral circuit descriptions.
Note: To prevent occurrence of unnecessary interrupts, the corresponding interrupt flag should be
cleared before setting the interrupt enable bit to 1 (interrupt enabled) and before terminating the
interrupt handler routine.

5.4 NMI

The watchdog timer embedded in this IC can generate a non-maskable interrupt (NMI). This interrupt takes prece-
dence over other interrupts and is unconditionally accepted by the CPU.
For detailed information on generating NMI, refer to the "Watchdog Timer" chapter.
S1C31W65 TECHNICAL MANUAL
(Rev. 1.1)
R/F converter Ch.0
interrupt
16-bit timer Ch.4 interrupt Underflow
16-bit timer Ch.5 interrupt Underflow
16-bit timer Ch.6 interrupt Underflow
16-bit timer Ch.7 interrupt Underflow
12-bit A/D converter
interrupt
– Reserved
-M0+ Interrupt Priority Registers (NVIC_IPR0–7). The priority
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Seiko Epson Corporation
Cause of hardware interrupt
• Reference oscillation completion
• Sensor A oscillation completion
• Sensor B oscillation completion
• Measurement counter overflow error
• Time base counter overflow error
• Analog input signal m A/D conversion
completion
• Analog input signal m A/D conversion result
overwrite error
-M0+ Devices Generic User Guide."
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5 INTERRUPT
Priority
Configurable
–
-M0+ Sys-
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5-3