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64 56K Interface circuit pack
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The SCC has two channels of high–speed–communication–designated COM
channel A and COM channel B. Under software control, it provides all
necessary control, status, and data functions for both the V.35 and RS–232
interfaces supported by the 56K XOVR circuit pack. Interface to the 56K
XOVR circuit pack is through the backplane via two 20 pin ribbon cables:
one 40–pin cable with two 20–pin connectors.
Replacing the 56K Interface circuit pack
Use the following procedure to replace this circuit pack.
297-1001-536 Standard 01.03 August 1996
Uses 64180 Z80 compatible CPU running at 6Mhz processor clock.
Industry standard two channel SCC chip running at 9.8304 Mhz. With
DMA interface, yields baud rates greater than 56K bps.
32K bytes of data RAM with plug–in sockets for up to an additional
512K bytes.
32K bytes to 64K bytes of boot PROM.
Support for V.35, 56Kbps/RS–232 (1200–9600 bps) selection on the
SCC ports.
Single error detection parity guard on entire static memory.
50 pin access port for logic analyzer, emulator and/or test support
(factory use only).
RS–232 compatible port for local diagnostics.
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