General Description - Northern Telecom BCS35 Replacement Manual

Card replacement guide, distributed processing peripheral
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56K Interface circuit pack – Turbo only

General description

The 56K Interface circuit pack in slot 7 provides a dual serial
communication interface function for the DPP. This circuit pack uses a
Serial Communication Controller (SCC) chip which lets the DPP transmit
and receive serial data at various standard software selectable programmed
rates from 1200–9600 bps on channel A and 56K bps on channel B.
56K Interface circuit pack communication with the Main processor (slot 1)
is based on a polling strategy as opposed to an interrupt scheme. Two FIFO
(First In–First Out) buffers provide a bidirectional path between the 56K
Interface circuit pack and Main processor.
The SCC port consists of an SCC chip (at U36) along with a bus interface
section and CPU interface section. The SCC has a 9.8304 MHz clock from
which it derives timing for SCC bus activity and SIO baud rates. A separate
clock is used because the clock available on the circuit pack (12 MHz)
exceeds chip capability. The 6MHz (12 MHz divided by two) provided by
the CPU is too slow for adequate SCC response.
Table 7–1 shows the five option jumpers on the circuit pack. Figure 7–1
shows jumper locations and circuit pack layout.
The 56K Interface circuit pack requires +5 V dc +/– 0.25 volts. This is
accomplished by the 5 volt regulator on the circuit pack which uses the +8.5
V dc supply from the backplane.
The 56K Interface circuit pack capabilities and functions include:
Interface between DPP system backplane and 56K XOVR circuit pack.
512 bytes of bidirectional FIFO RAM for data passing to/from main
CPU.
Noninterrupt driven (polled) data and command port implementation
allowing installation in any DPP COM (A7 and B7 used) slot without
any additional backplane wiring and capable of virtually simultaneous
access from either port without using WAIT states.
Host (main CPU side) interface to support fully asynchronous access
based on 4 mHz timing of standard Z80 bus cycle without wait states.
DPP Card Replacement Guide BCS35 and up
63

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Bcs36

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