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QSIO circuit pack
General description
Located in slot 6 of each chassis, the Quad Serial input/output
one port for maintenance terminal communications, one port for polling call
record data if 56K polling feature is unequipped, and two ports for the I/O
controllers for serial communication with the DMS–100 (MAP). Each port
maintains an independent, selectable baud rate for the transmit and receive
functions. On later release QSIOs the transmit clock may be generated
externally or internally. On the NT6M60AA QSIO, the receive clock can be
set for internal only. On the NT6M60BA QSIO, the receive clock can be set
for internal or external. See Table 6–1.
The QSIO circuit pack is a peripheral I/O device to the DPP on–line
processor. It provides an interface to system data, addresses, and control
signals. The eight–bit data bus is powered by a tristate octal bus transceiver
circuit under the active processor's control. The eight address lines are also
driven by the active processor, four of them buffered by a tristate octal
buffer. Another tristate octal buffer circuit buffers the ten control lines used
by the processor.
The QSIO circuit pack reports internal faults to the active processor by
generating signal interrupts. To minimize the signal's propagation delay
through the circuit pack, a bypass circuit is used in the Programmable Array
Logic (PAL). The interrupt output (–INT) is buffered by a quad z–input
positive NAND buffer chip to connect to the system interrupt line.
The QSIO circuit pack includes two dual baud rate circuits, plus circuitry to
select the clocking source. Each channel of the SIO chips requires two
separate clocks: one for transmit and one for receive. Either clock may be
generated internally on the circuit pack or externally. For externally
generated clocks, the SIO chips are fed by the two identical baud rate
circuits, each supporting a single SIO chip. Each circuit generates two baud
rate clocks. As a result, if internally generated clocks are selected, the
transmit and receive clocks for that channel must operate at the same rate,
since only one baud rate clock may be produced for each channel.
The settings on each SIO channel baud rate selector switch correspond to
different baud rates. These rates differ for synchronous and asynchronous
DPP Card Replacement Guide BCS35 and up
47
QSIO) has
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