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CHAPTER 3
CHAPTER 3
CHAPTER 3
CHAPTER 3
CHAPTER 3
CPU Pipeline Control
When this item is Enabled, only one pending cycle is allowed at one
time. When Disabled, there might be more than two pending cycles at one
time depending on the CPU behaviour.
PCI Delay Transaction
The chipset has an embedded 32-bit posted write buffer to support
delay transactions cycles. Select Enabled to support compliance with PCI
specification version 2.1. The settings are Enabled or Disabled.
Memory Parity Check
Enabled this item to test the boot-up memory.
AWARD
AWARD
AWARD
AWARD
AWARD
3-14
BIOS SETUP
BIOS SETUP
BIOS SETUP
BIOS SETUP
BIOS SETUP
®
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