Digital P.c.b. Block Diagram (1/2) - Panasonic DMR-BWT955GL Service Manual

11.4. Digital P.C.B. Block Diagram (1/2)

IC8202
CHIP CHANNEL RECEIVER
IF+_B IF+_B IF+_B IF+_B
TU8201
29 ADC_IP
4
IF-_B
TU8201
ADC_IN
30
5
SCL
TU8201
SCL_MAST
34
9
SDA
TU8201
33 SDA_MAST
8
TO
TUNER P.C.B.
IC8204
CHIP CHANNEL RECEIVER
IF-_A
TU8201
ADC_IN
30
15
IF+_A
TU8201
ADC_IP
29
14
SCL
TU8201
34 SCL_MAST
9
SDA
TU8201
SDA_MAST
33
8
IC51301
(8bit NAND)
64M X 8bit NAND
FLASH MEMORY
IC51001
(HDDEC/ENC/CPU/GFX Process/DDR3-IF/RTSC/AVCore/Graphics)
G_CH0PSYNC
TS_SYNC 8
A26 CH0PSYNC
G_CH0VAL
TS_VAL 7
C26 CH0VAL
CKG_CH0CLK
TS_CLK
9 B25 CH0CLK
G_CH0DATA
TS_DATA 11
B26 CH0DATA
G_SDA1_B
SDA_HOST
5
G_SCL1_B
SCL_HOST 4
XFERSTB
RESETB 22
G_SDA1_B
SDA_HOST
5 E26 SDA1
G_SCL1_B
SCL_HOST 4 F26 SCL1
XFERSTB
RESETB 22 D26 XFERST
G_CH1PSYNC
TS_SYNC
8 C28 CH1PSYNC
G_CH1VAL
TS_VAL
7 B28 CH1VAL
CKG_CH1CLK
TS_CLK
9 A27 CH1CLK
G_CH1DATA
TS_DATA 11
C27 CH1DATA
TC- 1 BUS_ED0-7_B
MM0CK
B12
MM0XCK
A12
MM1CK
K3
MM1XCK
K2
USB1DN
AF32 V33
USB1DP AG33 V33
USB2DN
AP11
USB2DP AN11
USB0DN AF34
USB0DP AF33
IC59001
( ETHERNET CONTROLLER)
11 MDIO
MDIO AP31
12 MDC
MDC AP33
22 TXC
RGMII_TXCLK AL33
HOST I/F 23 TXEN
RGMII_TXCTL AL32
24 TXD0
MII_TXD0 AM33
25 TXD1
MII_TXD1 AM32
26 TXD2
MII_TXD2 AN34
MII_TXD3 AN33 27 TXD3
HOST I/F
18 RXDV
RGMII_RXCTL AK31
19 RXC
RGMII_RXCLK AK33
MII_RXER AN32 20 RXER
13 RXD3
MII_RXD3 AK34
14 RXD2
MII_RXD2 AJ34
MII_RXD1 15 RXD1
AJ33
MII_RXD0 RXD0
AJ32 16
MDIO_INTL AP32 21 INTRP
XETH_RST AG29 10 REXT
83
IC52000
MM0DQ 0-15, MM0A0-14
DDR SDRAM
1Gbit
J7 CK
K7 /CK
IC52001
J7 CK
K7 /CK
DDR SDRAM
1Gbit
MM0DQ 16-31, MM0A 0-14
IC52203
MM1DQ 0-15, MM1A 0-13
DDR SDRAM
1Gbit
J7 CK
K7 /CK
P59304
3
P59304
2
PW_5V_VBUS_2
TX+
TXP 7
TX-
TXM
6
RX+
5
RXP
RX-
RXM
4
DMR-BWT955GL
DIGITAL BLOCK DIAGRAM(1/2)
VIDEO REC SIGNAL
VIDEO EE SIGNAL
VIDEO PB SIGNAL
AUDIO REC SIGNAL
AUDIO EE SIGNAL
AUDIO PB SIGNAL
WIRELESS
MODULE
P59302
(Front USB)
3 DP
2 DN
VBUS
1
JK59001
ETHERNET & USB JACK
12
13
2 TX+
3 TX-
RX+
4
5 RX-