Ieee1394 I/F (Aj-Yad120Ag) Block Diagram - Panasonic DVCPRO HD EX AJ-HD1200AP Service Manual

IEEE1394 I/F (AJ-YAD120AG) BLOCK DIAGRAM

P500 <11>
IP503 <11>
IC502 <11>
MB29LV160
(FLASH
(FPGA CONFIG)
MEMORY)
IC250 <6>
P250 <6>
TPA0
TPA0
EXTENSION
1394 PROCESS
TPA1
CONNECTOR
TPB1
IC300 <7>
IC301 <7>
PIX_A,B
PP_DATA
PREP50
SDRAM
PP_CTRL
(FPGA)
SD_DATA[0-7]
PREP_Y,C FLT_Y,C
IC350 <8>
FILTER
JTAG
PROG_B, INIT B,
IC200 <5>
CCLK, DONE
TE7720
CONF_STATUS
SDRAM(256M)
[0-2]
PLIF_CTRL [0-1]
PLIF_D [0-7]
X250 <6>
XTAL
24.576MHz
IC450 <10>
IC400 <9>
COMP_AUD
12,34
COMP100
COMP_A,B
AUX
X550, IC557 <12>
XTAL
72MHz
IC150 <4>
CONF_STATUS
[0-2]
UP_A[1-19]
FPGA (DUEL) 1394
UP_D[0-15]
UP_A[1-19]
UP_D[0-15]
BUS CTRL
(FPGA)
1394_SSP, FRP
AUDIO [0-1], AUDIO FRM
IEEE1394 I/F CIRCUIT
IC55 <2>
AK6480AF
(EEPROM)
IC50 <2>
IC51 <2>
UP_RST_L
RESET
GEN
MICROPROCESSOR
P50 <2>
FLASH ROM
CONNECTOR
IC100 <3>
DPRAM
IDT71V321
IC1-5 <1>
+3.3V_A
+2.5V_A
REG.
+1.8V_A,C
+1.5V_B
1394_SSP, FRP
AUDIO [0-1], AUDIO FRM
SD_DATA[0-7]
REC PB
CIRCUIT
P1 P300
RESET
B17
DP DATA
B7, A/B8-9, A11
DP ADRS
A/B2-6, A7
A/B44-49
A/B39
A/B29, B30
A/B39-42