Momentary Mute Circuit - Sanyo AVM-2550S Training Manual

The Momentary Mute circuit is provided to prevent buzz or static in the
speakers when changing channels. The momentary mute circuit operates
when the power key is pressed, when changing channels, when switching
Antenna mode, when searching channels, when changing MTS or TV/AV
modes, when switching Surround On/Off mode, and when exchanging
programs between the main screen and PIP window. The momentary mute
should not be confused with the normal mute function performed by pressing
the MUTE key on the remote control. The momentary mute operates for a
period of 0.2 to 1.6 seconds depending on the operation being performed.
The momentary mute is controlled by the BUS control signal and the Mute
signal from the CPU: the BUS SDA (Serial Data) signal from pin 32, the BUS
SCL (Serial Clock) signal from pin 34, and the Mute signal from pin 38.
STA
(MSB)
D7 D6 D5 D4 D3
1 0 0 0 0
IC WRITE ADDRESS
(MSB)
D7 D6 D5 D4 D3
1 0 0 0 0
IC WRITE ADDRESS
(MSB)
D6
D5 D4 D3
D7
1 0 0 0 0
IC WRITE ADDRESS

MOMENTARY MUTE CIRCUIT

ICW SUB
(LSB) (MSB)
D2
D1 D0 D6
D7
0 0
1 0 0
(MSB)
(LSB)
D2 D1 D0 D6
D7
0 0
1 0 0
(LSB) (MSB)
D2 D7
D1 D0 D6
1 0 0
0 0
BUS Data Format in Write Mode - Momentary Mute Operation
When changing channels, the CPU will output the BUS control signals and the
Mute signal to perform the momentary mute. The BUS control signals from
the CPU are input to the BUS Interface circuit within IC3401, the MTS
Processor. The BUS interface circuit will write a 6-bit data "000000" into each
of the Volume Control Registers and a 1 bit data "0" into each of the Audio
Mute Control Registers to minimize the output level at pins 3, 4, 38 and 39 of
IC3401. In addition the Mute (High) is coupled to the base of Q001, switching
Q001 On, grounding pin 5 of IC001. The minimum output level at pins 3, 4,
38 and 39 of IC3401 and the Low at pin 5 of IC001 will mute the audio output
of the Audio Amplifier IC001 and the external audio equipment, preventing
buzz or static in the speakers. Once the operation is complete, the CPU will
output the BUS control signal and the Mute (Low) signal to restore the output
sound level, allowing the audio to return to normal.
DA
(LSB)
D5 D4 D3 D2 D1
0 0 0 0 1
SUB. ADDRESS
(LSB)
D5 D4 D2 D1
D3
0 0 0 1 1
SUB. ADDRESS
(LSB) (MSB)
D5 D4
D3 D2 D1
0 0 1 0 0
SUB. ADDRESS
– 30 –
STO
(MSB)
D0 DA7 DA6 DA5 DA4 DA3
1
0 0 0
Don't
EXT2 NRSW FOMO SAPC
M2 EXT1
care bit
(MSB)
D0 DA7 DA6 DA5 DA4 DA3
1 0 0
Don't care bits
DA7
D0 DA6 DA5 DA4 DA3
0 0 0
Don't care bits
STA: START Condition
ICW: IC Address + Write
SUB: Sub. Address
DA : Data
STO: STOP Condition
(LSB)
DA2 DA1 DA0
0 0 0 0
M1
(LSB)
DA2 DA1 DA0
0 0 0 0
VOL-L
(LSB)
DA2
DA1 DA0
0 0 0 0
VOL-R