Pll Data Out Circuit - Sanyo AVM-2550S Training Manual

The VB7C chassis uses a new BUS-Controlled UHF/VHF Tuner with a built-
in Phase Locked Loop, Prescaler and Band Switch. Including these circuits
in the tuner reduced RF radiation and simplified shielding requirements and
printed wiring board layout. The primary difference between this chassis and
the previous chassis (C-983) is the exclusive PLL control lines (PLL Enable,
PLL Data, PLL Clock) are unified to the common BUS control lines (BUS SDA,
BUS SCL), and the BUS control program is incorporated in the CPU (C-003).
IC801
CPU
BUS
SDA
BUS
SCL

PLL DATA OUT CIRCUIT

L881
R881
32
L882
R882
34
PLL Data Circuit
Channel selection requires only two inputs from the CPU. These are the Data
signal input from pin 32, and the Clock signal input from pin 34. The Data
signal controls the band switching, the channel selection and the AFT. The
channel selection and the AFT function are controlled by changing the divide
ratio for the PLL.
The tuning data format is composed of 5 byte data. See Tuning Data Format
figure below.
R856
R857
– 10 –
A101
TUNER
DATA
CLOCK