Sharp HT-DV40H Service Manual page 109

Symbol Pin #
UA0_TX/GPIO 206
V_COMP 207
V_BIAS 208
V_FSADJ 209
V_REFOUT 210
V_DAC[0] 211
V_DAC[1] 214
V_DAC[2] (or NC) 215
V_DAC[3] (or NC) 218
V_DAC[4] 219
V_DAC[5] 221
NC 223
R_A20/GPIO 225
R_A21/GPIO 226
Input/Output
Input/Output UART #0 data transmit or GPIO
Priority selection
gpio_first[3][13] = 1
sft_cfg2[3:2] = 1
sft_cfg3[13:12] = 1
sft_cfg14[10:8] = 3'b011
sft_cfg4[15:13] = 3'b011
(other)
Compensation pin. A 0.1pF ceramic capacitor must be used to bypass this pin to
A VSSA.
The lead length must be kept as short as possible to avoid noise.
Full-Scale adjustment control pin. The full-scale current of D/A converters can be
A
adjusted by connecting a resistor (R
Voltage reference output. It generates typical 1.2V voltage reference and may be
A
used to drive V_REFIN pin directly.
Video DAC output #0. This is a high-impedance current source output. These
A
outputs can drive a 37.5Ω load directly.
Video DAC output #1. This is a high-impedance current source output. These
A
outputs can drive a 37.5Ω load directly.
Video DAC output #2. This is a high-impedance current source output. These
A
outputs can drive a 37.5Ω load directly. NC for SPHE8281A-256.
Video DAC output #3. This is a high-impedance current source output. These
A
outputs can drive a 37.5Ω load directly. NC for SPHE8281A-256.
Video DAC output #4. This is a high-impedance current source output. These
A
outputs can drive a 37.5Ω load directly.
Video DAC output #5. This is a high-impedance current source output. These
A
outputs can drive a 37.5Ω load directly.
- No connection
Input/Output
ROM / SRAM / flash address bus bit [20], or GPIO[92]
Priority selection
gpio_first[5][12] = 1
PINMUX_control[0][1] = 1
{sft_cfg20[0],sft_cfg7[5:4]} = 3'b010 656_DATA[7]
{sft_cfg20[1],sft_cfg19[5:4]} = 3'b010 HD_DATA[7]
{sft_cfg20[2],sft_cfg14[7:6]} = 3'b010 SRGB_DATA[7]
sft_cfg11[5:3] = 3'b110
sft_cfg0[13:12] = 3
sfg_cfg16[15:12] = 4'b0010
sfg_cfg16[15:12] = 4'b0110
sfg_cfg18[3:0] = 4'b1000
(other)
Input/Output
ROM / SRAM / flash address bus bit [21], or GPIO[93]
Priority selection
gpio_first[5][13] = 1
PINMUX_control[0][2] = 1
{sft_cfg20[0],sft_cfg7[5:4]} = 3'b010 656_DATA[6]
{sft_cfg20[1],sft_cfg19[5:4]} = 3'b010 HD_DATA[6]
{sft_cfg20[2],sft_cfg14[7:6]} = 3'b010 SRGB_DATA[6]
sft_cfg11[5:3] = 3'b110
sft_cfg0[13:12] = 3
sfg_cfg16[11:8] = 4'b0110
sfg_cfg16[15:12] = 4'b0010
sfg_cfg18[3:0] = 4'b1000
(other)
8 – 24
Description
Function
GPIO[61]
UA0_TXD (default)
TV_VSYNC
TV_VDSYNC_SRGB
TV_VSYNC_PC
GPIO[61]
) between this pin and ground.
SET
Function
GPIO[92]
ROM_ADDR[20] (default) Output
TS_GNT_B
TV_LCD_B[0]
FM_GPIOB[14]
FM_GPIOB[12]
FM_GPIOB[34]
GPIO[92]
Function
GPIO[93]
ROM_ADDR[21] (default) Input/Output
TS_FRAME_B
TV_LCD_B[1]
FM_GPIOB[11]
FM_GPIOB[15]
FM_GPIOB[33]
GPIO[93]
HT-DV40H
Dir
Input/Output
Input
Input/Output
Output
Output
Input/Output
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Input/Output
Output
Output
Output
Input/Output
Output
Input/Output
Input/Output
Input/Output
Input/Output
Dir
Input/Output
Output
Output
Output
Input/Output
Output
Input/Output
Input/Output
Input/Output
Input/Output