Table of Contents
Advertisement
Signal Name
Type
G_DEVSEL#
I/O
G_ DEVSEL#: Device Select.
s/t/s
During PIPE# and SBA Operation: This signal is not used during PIPE# or SBA
AGP
operation.
During FRAME# Operation: G_DEVSEL#, when asserted, indicates that a
FRAME#-based AGP target device has decoded its address as the target of the
current access. The MCH asserts G_DEVSEL# based on the SDRAM address
range being accessed by a PCI initiator. As an input, G_DEVSEL# indicates
whether the AGP master has recognized a PCI cycle to it.
G_REQ#
I
G_REQ#: Request.
AGP
During SBA Operation: This signal is not used during SBA operation.
During PIPE# and FRAME# Operation: G_REQ#, when asserted, indicates that
the AGP master is requesting use of the AGP interface to run a FRAME#- or
PIPE#-based operation.
G_GNT#
O
G_GNT#: Grant.
AGP
During SBA, PIPE# and FRAME# Operation: G_GNT#, along with the information
on the ST[2:0] signals (status bus), indicates how the AGP interface will be used
next. Refer to the AGP Interface Specification, Revision 2.0 for further explanation
of the ST[2:0] values and their meanings.
G_AD[31:0]
I/O
G_AD[31:0]: Address/Data Bus.
AGP
During PIPE# and FRAME# Operation: The G_AD[31:0] signals are used to
transfer both address and data information on the AGP interface.
During SBA Operation: The G_AD[31:0] signals are used to transfer data on the
AGP interface.
G_CBE[3:0]#
I/O
Command/Byte Enable.
AGP
During FRAME# Operation: During the address phase of a transaction, the
G_CBE[3:0]# signals define the bus command. During the data phase, the
G_CBE[3:0]# signals are used as byte enables. The byte enables determine which
byte lanes carry meaningful data. The commands issued on the G_CBE# signals
during FRAME#-based AGP transactions are the same G_CBE# command
described in the PCI 2.2 specification.
During PIPE# Operation: When an address is enqueued using PIPE#, the C/BE#
signals carry command information. Refer to the AGP 2.0 Interface Specification,
Revision 2.0 for the definition of these commands. The command encoding used
during PIPE#-based AGP is different than the command encoding used during
FRAME#-based AGP cycles (or standard PCI cycles on a PCI bus).
During SBA Operation: These signals are not used during SBA operation.
G_PAR
I/O
Parity.
AGP
During FRAME# Operation: G_PAR is driven by the MCH when it acts as a
FRAME#-based AGP initiator during address and data phases for a write cycle, and
during the address phase for a read cycle. G_PAR is driven by the MCH when it
acts as a FRAME#-based AGP target during each data phase of a FRAME#-based
AGP memory read cycle. Even parity is generated across G_AD[31:0] and
G_CBE[3:0]#.
During SBA and PIPE# Operation: This signal is not used during SBA and PIPE#
operation.
PCIRST# from the ICH4-M is assumed to be connected to RSTIN# and is used to reset AGP interface
logic within the MCH. The AGP agent will also typically use PCIRST# provided by the ICH4-M as an
input to reset its internal logic.
2.5.
Clocks, Reset, and Miscellaneous
Table 12. Clocks, Reset, and Miscellaneous Signal Descriptions
Signal Name
Type
BCLK
I
Differential Host Clock In: These pins receive a differential host clock from the
CMOS
external clock synthesizer. This clock is used by all of the MCH logic that is in the
BCLK#
Host clock domain.
66IN
I
66 MHz Clock In: This pin receives a 66-MHz clock from the clock synthesizer.
CMOS
This clock is used by AGP/PCI and hub interface clock domains.
NOTE: That this clock input is 3.3-V tolerant.
SCK[5:0]
O
SDRAM Differential Clock (DDR): These signals deliver a source synchronous
CMOS
clock to the SO-DIMMs. There are three per SO-DIMM.
SCK#[5:0]
O
SDRAM Inverted Differential Clock (DDR): These signals are the complement to
CMOS
the SCK[5:0] signals. There are three per SO-DIMM.
RSTIN#
I
Reset In: When asserted this signal will asynchronously reset the MCH logic. This
CMOS
signal is connected to the PCIRST# output of the ICH4-M. All AGP/PCI output and
bi-directional signals will also tri-state compliant to PCI Rev 2.0 and 2.1
specifications.
NOTE: That this input needs to be 3.3-V tolerant.
TESTIN#
I
Test Input: This pin is used for manufacturing and board level test purposes.
CMOS
NOTE: This signal has an internal pullup resistor.
DPSLP#
I
Deep Sleep Input: This signal comes from the ICH4-M device, providing an
CMOS
indication of C3 and Deeper Sleep (C4) state entry to the CPU.
NOTE: that this input is low-voltage CMOS, operating on the PSB Vccp power
plane.
ETS#
I
External Thermal Sensor Input: This signal is an active low input to the MCH,
CMOS
which is used to monitor status of external thermal sensor activity, is enabled. The
MCH can be optionally programmed to send a SERR, SCI, or SMI message to
ICH4-M upon the triggering of this signal.
2.6.
Description
Description
9.2.
1-36
Voltage References, PLL Power
Table 13. Voltage References, PLL Power Descriptions
Signal Name
Type
HLRCOMP
I/O
Compensation for hub interface: This signal is used to calibrate the hub
CMOS
interface I/O buffers.
GRCOMP
I/O
Compensation for AGP: This signal is used to calibrate AGP buffers.
CMOS
HRCOMP[1:0]
I/O
Compensation for Host: This signal is used to calibrate the Host AGTL+ I/O
CMOS
buffers.
SMRCOMP
I/O
System Memory RCOMP
CMOS
HVREF[4:0]
Host Reference Voltage. Reference voltage input for the Data, Address, and
Common clock signals of the Host AGTL+ interface
SMVREF[1:0]
DDR Reference Voltage: Reference voltage input for DQ, DQS, and RCVENIN#.
HI_REF
Hub Interface Reference: Reference voltage input for the hub interface.
AGPREF
AGP Reference: Reference voltage input for the AGP interface.
HSWNG[1:0]
Host Reference Voltage: Reference voltage input for the compensation logic.
VCC1_2
The 1.2 V Power input pins
VCC1_8
The 1.8 V Power input pins
VCCSM
The DRAM Power input pins. 2.5 V for DDR.
VCC1_5
The power supply input for the AGP I/O supply (1.5 V)
VCCGA,
PLL power input pins. (1.8 V)
VCCHA
VCCP
The AGTL+ bus termination voltage inputs (1.05 V)
VSS
GROUND
The following table shows the value of the RCOMP resistor and the termination point for each
interface's RCOMP signal.
Note: These values are based on the board impedance assumption of 55 Ohm ± 15%.
Table 14. RCOMP Resistor Value Recommendations
Interface
RCOMP R
Host PSB
27.4 Ohm ± 1%
AGP
36.5 Ohm ± 1%
Hub Interface
39.4 Ohm ± 1%
SM DDR
30.1 Ohm ± 1%
Ballout Table
Signal Name
Ball#
Signal Name
ADS#
U7
G_AD21
AD_STB0
R24
G_AD22
AD_STB1
AC27
G_AD23
AD_STB0#
R23
G_AD24
AD_STB1#
AC28
G_AD25
AGPREF
AA21
G_AD26
BNR#
V3
G_AD27
BPRI#
Y7
G_AD28
BR0#
V7
G_AD29
CPURST#
AE17
G_AD3
DBSY#
V5
G_AD30
DEFER#
Y4
G_AD31
DBI0#
AD5
G_AD4
DBI1#
AG5
G_AD5
DBI2#
AH9
G_AD6
DBI3#
AD15
G_AD7
DPSLP#
V8
G_AD8
DPWR#
Y8
G_AD9
DRDY#
W2
G_CBE0#
G_AD0
R27
G_CBE1#
G_AD1
R28
G_CBE2#
G_AD10
T23
G_CBE3#
G_AD11
U23
66IN
G_AD12
T24
G_DEVSEL#
G_AD13
U24
G_FRAME#
G_AD14
U25
G_GNT#
G_AD15
V24
G_IRDY#
G_AD16
Y27
G_PAR
G_AD17
Y26
GRCOMP
G_AD18
AA28
G_REQ#
G_AD19
AB25
G_STOP#
G_AD2
T25
G_TRDY#
G_AD20
AB27
HA10#
VGN-S36C/S36GP/S36LP/S36SP/S36TP/S38CP/S52B/
S62PS/S62PSY/S62S/S350F/S350FP/S360/S360P/S370F
IC
Description
RCOMP Term
VSS
VSS
VCC1_8
V1.25
(1.25 V Vtt for DDR)
Ball#
Signal Name
Ball#
AA27
HA11#
P3
AB26
HA12#
P5
Y23
HA13#
R6
AB23
HA14#
N2
AA24
HA15#
N5
AA25
HA16#
N3
AB24
HA17#
J3
AC25
HA18#
M3
AC24
HA19#
M4
R25
HA20#
M5
AC22
HA21#
L5
AD24
HA22#
K3
T26
HA23#
J2
T27
HA24#
N6
U27
HA25#
L6
U28
HA26#
L2
V26
HA27#
K5
V27
HA28#
L3
V25
HA29#
L7
V23
HA3#
U6
Y25
HA30#
K4
AA23
HA31#
J5
P22
HA4#
T5
W28
HA5#
R2
Y24
HA6#
U3
AH25
HA7#
R3
W27
HA8#
P7
W25
HA9#
T3
AD25
HADSTB0#
R5
AG24
HADSTB1#
N7
W23
BCLK#
K8
W24
BCLK
J8
P4
HD0#
AA2
Confidential
(J/AM/AO)
Advertisement
Table of Contents
