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Pin 44, VID1: One of the six logic VID pins to program the output
voltage.
Pin 45, VID2: One of the six logic VID pins to program the output
voltage.
Pin 46, VID3: One of the six logic VID pins to program the output
voltage.
Pins 47, NC: No connect.
Pins 48, NC: No connect.
Block Diagram
1.255V
async.
POR
PSI#
-
+
por
+
uv lo
VDD
-
1.255V
1.255V
P_Z1
BG
DPSLP#
Bias
Mode
P_Z0
Logic
DPRSLP
mode
VDAC
VID0
1.708V
VID1
drv1_enable
Logic
50ns
VID2
6-Bit
drv2_enable
DAC
VID3
VID4
-
+
VID5
mode
VDPSLP
enable#
VBOOT
VDPRSLP
+
-
-
+
VID0-5
-
S S
+
mode
0.2V
5 V
5 V
ih
V1R7
-
+
1.708V
soft_off
S>R
20µs
enable
R
Q
VR_ON
Delay
S
Q
TGND
6ms
SGND
Delay
CLK_EN#
Electrical Characteristics
Specifications with standard typeface are for T
= 25
J
o
o
temperature range of -5
C to +110
C. VDD = 5V, SGND = DGND = PGND1 = 0V, unless otherwise stated.
(Notes 4)
Symbol
Parameter
Conditions
Chip Supply
VDD Shutdown Current
VR_ON = 0V, VDD = 6V.
VDD Normal Operating
VR_ON = 3.3V.
Current
UVLO Threshold
VDD = V5A = V5B, rising from 0V.
VDD = V5A = V5B falling from
UVLO Hysteresis
UVLO Threshold.
Logic
VR_ON, DPSLP#,
VR_ON, DPSLP#, MCH_OK or
MCH_OK and DPRSLP
DPRSLP rising from 0V.
Input Logic High
VR_ON, DPSLP#,
VR_ON, DPSLP#, MCH_OK or
MCH_OK and DPRSLP
DPRSLP falling from 3.3V.
Input Logic Low
CLK_EN# Sink Current
CLK_EN# = 0.1V and asserted.
Power Good
Power Good Upper
Threshold As A Percent-
SENSE voltage rising from 0V.
age of VREF
Power Good Lower
SENSE voltage falling from above
Threshold As A Percent-
VREF.
age of VREF
Hysteresis
Power Good Delay
PGOOD Sink Current
PGOOD = 0.1V and asserted.
Output Voltage Slew Rate Control
Soft Start Current
SS = 0V.
Soft Shutdown Current
SpeedStep¥ and Mode
Change Slew Rate Con-
SYNC1
1.708V
SYNC2
vid_change
async.
1-Phase
Logic
PGND1
drv1_enable
soft_start
SW1
OUT1
OUT2
current_lim#
SET
Q
D
drv2_enable
Q
CL R
current_lim#
enable#
VREF
phase
5 V
ILIM1
ILIM2
0.5 x ih
ILIMREF
current_lim
phase
ih
2.5 x ih
CMP1
5 V
CMP2
CMPREF
XOR
100 µs
PGOOD
Edge
Delay
Circuit
DGND
SENSE
VO VP
+
.88
-
-
O V
+
+
.80
-
enable#
Q
R
ov p
Q
S
20µ s
Delay
MCH_OK
o
C, and those with boldface type apply over a junction
Min
Typ
Max
Units
µA
10
1
3.0
4.2
mA
3.9
4.1
4.3
V
0.2
0.35
V
2.31
1.9
V
1.43
0.99
V
2
3.2
mA
108
112
116
%
84.5
87
90.5
%
2
%
µs
3.6
2
3
mA
µA
16
22
32
µA
33
45
57
µA
255
335
415
trol Current
DAC and References
VID Pins Input Logic High
VID Pins Input Logic Low
Measured at VREF pin.
-5
°
C < Tj < 85
DAC codes from 0.844V to 1.708V.
DAC Accuracy
DAC codes from 0.700V to 0.828V.
-5
°
C < Tj < 110
DAC codes from 0.844V to 1.708V.
DAC codes from 0.700V to 0.828V.
V1R7 Accuracy
17kΩ from V1R7 to GND.
VDPSLP = 1.398V, Measured at
VDPSLP Offset
VREF pin.
VBOOT = 1.00V, Measured at
VBOOT Offset
VREF pin.
VDPRSLP = 0.748V, Measured at
VDPRSLP Offset
VREF pin.
source
VREF Driving Capability
sink
source
VDAC Driving Capability
sink
V1R7 Driving Capability
source
Error Comparator
Error Comparator Input
CMP1 = CMP2 = 1.436V.
Bias Current (Sourcing)
Error Comparator Input
CMPREF = 1.436V.
Offset Voltage
R
= 17kΩ
hys
Hysteresis Current
R
= 170kΩ
hys
Error Comparator Propa-
20mV overdrive
gation Delay
Current Limit
Current Limit Comparator
Input Bias Current
Current Limit Comparator
ILIMREF = 1.436V.
Input Offset Voltage
R
= 17kΩ, ILIMREF < ILIMx
hys
Current Limit Setting Cur-
R
= 17kΩ, ILIMREF > ILIMx
hys
rent
R
= 170kΩ, ILIMREF < ILIMx
hys
Time Delays
VBOOT Voltage Holdup
From assertion of MCH_OK to as-
t
BOOT
Time
sertion of CLK_EN#.
Power Good Mask For
From assertion of CLK_EN# to as-
t
CPU_PWRGD
Initial VID Voltage Settling
sertion of PGOOD.
Power Good Mask For
SpeedStep¥ Change
Power Good De-assertion
Delay From VR_ON de-assertion to
Delay Upon Shutdown
PGOOD de-assertion
Over-voltage Protection
SENSE Voltage As A
VOVP = VREF
Percentage of VOVP
System
PSI# Input Logic High
PSI# Input Logic Low
PSI# Pin Leakage Current PSI# = 7.5V
Soft Shutdown Finish
Threshold
Note 1: Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating Ratings are
conditions under which operation of the device is guaranteed. For guaranteed performance limits and associated test
conditions, see the Electrical Characteristics table. Functional temperature range is the range within which the device
performs its intended functions, but not necessarily meeting the limits specified in the Electrical Characteristic table.
Note 2: The maximum allowable power dissipation is calculated by using P
is the ambient temperature, and θ
maximum junction temperature, T
A
the specified package. The 1.56W rating results from using 150°C, 25°C, and 80°C/W for T
A θ
of 90°C/W represents the worst-case condition of no heat sinking of the 48-pin TSSOP. Heat sinking allows the
JA
safe dissipation of more power. The Absolute Maximum power dissipation should be derated by 12.5mW per °C above
25°C ambient. The LM2729 actively limits its junction temperature to about 150°C.
Note 3: For detailed information on soldering plastic small-outline packages, refer to the Packaging Databook available
from National Semiconductor Corporation.
Note 4: All limits are guaranteed. All electrical characteristics having room-temperature limits are tested during produc-
tion with T
= T
= 25°C. All hot and cold limits are guaranteed by correlating the electrical characteristics to process and
A
J
temperature variations and applying statistical process control.
VGN-S36C/S36GP/S36LP/S36SP/S36TP/S38CP/S52B/
S62PS/S62PSY/S62S/S350F/S350FP/S360/S360P/S370F
1-20
0.63
0.315
°
C
-1.0
+1.0
-1.3
+1.3
°
C
-1.3
+1.3
-1.5
+1.5
-1.674
1.708
+1.742
-4.5
+4.5
-4.5
+4.5
-4.5
+4.5
1.5
11.7
1.4
14.3
580
12
21
38
-2
+2
82
98
115
10
70
9
21
35
-2
+2
255
294
345
250
30
10
18
30
3
5
9
100
179
133
90
109
123
139
0.63
0.315
100
0.3
= (T
- T
)/θ
, where T
Dmax
Jmax
A
JA
Jmax
is the junction-to-ambient thermal resistance of
JA
, and θ
, T
respectively.
Jmax
A
JA
Confidential
(J/AM/AO)
IC
V
V
%
V
mV
mV
mV
mA
mA
mA
mA
µA
µA
mV
µA
µA
ns
µA
mV
µA
µA
µA
µs
ms
µs
ns
%
V
V
µA
V
is the
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