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AC CHARACTERISTICS - I (continue)
Parameter
Symbol
Row Cycle Time
t
RC
Auto Refresh Row Cycle Time
t
RFC
Row Active Time
t
RAS
Row Address to Column Address Delay for Read
t
RCDRD
Row Address to Column Address Delay for Write
t
RCDWR
Row Active to Row Active Delay
t
RRD
Column Address to Column Address Delay
t
CCD
Row Precharge Time
t
RP
Write Recovery Time
t
WR
Last Data-In to Read Command
t
DRL
Auto Precharge Write Recovery + Precharge Time
t
DAL
CL=5
System Clock Cycle Time
CL=4
t
CK
CL=3
Clock High Level Width
t
CH
Clock Low Level Width
t
CL
Data-Out edge to Clock edge Skew
t
AC
DQS-Out edge to Clock edge Skew
t
DQSCK
DQS-Out edge to Data-Out edge Skew
t
DQSQ
Data-Out hold time from DQS
t
QH
Clock Half Period
t
HP
Data Hold Skew Factor
t
QHS
Input Setup Time
t
IS
Input Hold Time
t
IH
Write DQS High Level Width
t
DQSH
Write DQS Low Level Width
t
DQSL
Clock to First Rising edge of DQS-In
t
DQSS
Data-In Setup Time to DQS-In (DQ & DM)
t
DS
Parameter
Symbol
Data-In Hold Time to DQS-In (DQ & DM)
t
DH
Read DQS Preamble Time
t
RPRE
Read DQS Postamble Time
t
RPST
Write DQS Preamble Setup Time
t
WPRES
Write DQS Preamble Hold Time
t
WPREH
Write DQS Postamble Time
t
WPST
Mode Register Set Delay
t
MRD
Exit Self Refresh to Any Execute Command
t
XSC
Power Down Exit Time
t
PDEX
Average Periodic Refresh Interval
t
REFI
Note :
1.
This calculation accounts for tDQSQ(max), the pulse width distortion of on-chip circuit and jitter.
2.
Data sampled at the rising edges of the clock : A0~A11, BA0~BA1, CKE, /CS, /RAS, /CAS, /WE.
3.
Data latched at both rising and falling edges of Data Strobes(DQS0~DQS3) : DQ, DM(0~3).
4.
Minimum of 200 cycles of stable input clocks after Self Refresh Exit command, where CKE is held high, is required to complete
Self Refresh Exit and lock the internal DLL circuit of DDR SDRAM.
5.
Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this
value can be greater than the minimum specification limits for tCL and tCH).
6.
tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL).
tQHS consists of tDQSQmax, the pulse width distortion of on-chip clock circuits, data pin to pin skew and
output pattern effects, and p-channel to n-channel variation of the output drivers.
7.
DQS, DM and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times.
Signal transitions through the DC region must be monotonic.
AC CHARACTERISTICS - II
Frequency
CL
tRC
tRFC
tRAS
500MHz (2ns)
5
23
26
450MHz (2.2ns)
5
21
24
400MHz (2.5ns)
5
18
21
350MHz (2.8ns)
5
16
17
300MHz (3.3ns)
4
14
17
275MHz (3.6ns)
4
14
16
250MHz (4.0ns)
4
13
15
28
33
36
Unit
Min
Max
Min
Max
Min
Max
CK
16
-
14
-
14
-
17
-
17
-
16
-
CK
CK
10
120K
9
120K
9
120K
5
-
5
-
5
-
CK
CK
2
-
2
-
2
-
4
-
3
-
3
-
CK
CK
1
-
1
-
1
-
5
-
5
-
5
-
CK
3
-
3
-
3
-
CK
CK
2
-
2
-
2
-
8
-
8
-
8
-
CK
ns
2.8
6
-
-
-
-
-
-
3.3
10
3.6
10
ns
ns
-
-
4.5
10
4.5
10
0.45
0.55
0.45
0.55
0.45
0.55
CK
CK
0.45
0.55
0.45
0.55
0.45
0.55
-0.6
0.6
-0.6
0.6
-0.6
0.6
ns
ns
-0.6
0.6
-0.6
0.6
-0.6
0.6
-
0.35
-
0.35
-
0.4
ns
tHPmin
tHPmin
tHPmin
-
-
-
ns
-tQHS
-tQHS
-tQHS
tCH/L
tCH/L
tCH/L
ns
-
-
-
min
min
min
ns
-
0.35
-
0.35
-
0.4
0.75
-
0.75
-
0.75
-
ns
ns
0.75
-
0.75
-
0.75
-
0.4
0.6
0.4
0.6
0.4
0.6
CK
0.4
0.6
0.4
0.6
0.4
0.6
CK
0.85
1.15
0.85
1.15
0.85
1.15
CK
0.35
-
0.35
-
0.4
-
ns
28
33
36
Unit
Min
Max
Min
Max
Min
Max
ns
0.35
-
0.35
-
0.4
-
0.9
1.1
0.9
1.1
0.9
1.1
CK
CK
0.4
0.6
0.4
0.6
0.4
0.6
0
-
0
-
0
-
ns
CK
0.35
-
0.35
-
0.35
-
0.4
0.6
0.4
0.6
0.4
0.6
CK
CK
2
-
2
-
2
-
200
-
200
-
200
-
CK
2tCK
2tCK
1tCK
-
-
-
CK
+ tIS
+ tIS
+ tIS
us
-
7.8
-
7.8
-
7.8
tRCDRD
tRCDWR
tRP
tDAL
Unit
16
7
4
7
11
tCK
14
7
3
7
11
tCK
12
6
3
6
9
tCK
10
5
2
5
8
tCK
9
5
2
5
8
tCK
9
5
2
5
8
tCK
8
5
2
5
8
tCK
HYB25D128323C-3.3 (INFINEON)
MEMORIES FOR GRAPHICS SYSTEMS
Note
1
2
3
4
DQS
DM
DQ
V
A
0
0
SSQ
DQ
V
V
NC
B
4
DDQ
DDQ
DQ
DQ
V
V
C
6
5
SSQ
SSQ
DQ
V
V
V
D
7
DD
SS
DDQ
DQ
DQ
V
V
E
17
16
DDQ
SSQ
DQ
DQ
V
V
F
19
18
SSQ
DDQ
DQS
DM
V
G
NC
2
2
SSQ
DQ
DQ
V
V
H
21
20
SSQ
DDQ
DQ
DQ
V
V
J
22
23
DDQ
SSQ
V
V
CAS#
WE#
K
DD
SS
1,6
BA
L
RAS#
NC
NC
1,5
BA
A
M
CS#
NC
6
0
0
2
2
1.5
Signal and Pin Description
3
Table 2
Signal and Pin Description
Pin
IO Type
Clock: CLK and CLK# are differential clock inputs. All address and command inputs are latched on the
CLK, CLK#
Input
crossing of the positive edge of CLK and the negative edge of CLK#. Output data (DQ's and DQS) is
referenced to the crossing of CLK and CLK#.
Clock Enable: CKE HIGH activates and CKE LOW deactivates the internal clock, input buffers and
Note
output drivers. Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF REFRESH
operations (all banks idle), or ACTIVE POWER-DOWN (row active in any bank). CKE is synchronous
for POWER-DOWN entry and exit, and for SELF REFRESH entry. CKE is asynchronous for SELF-
3
CKE
Input
REFRESH exit. CKE must be maintained HIGH trough out READ and WRITE accesses. Input buffers
(excluding CLK, CLK#) are disabled during POWER-DOWN. Input buffers (excluding CKE) are
disabled during SELF REFRESH. CKE is an SSTL2 input but will detect an LVCMOS LOW level after
VDD is applied.
Chip Select: CS# enables the command decoder when low and disables it when high. When the
CS#
Input
command decoder is disabled, new commands are ignored, but internal operations continue. CS# is
considered part of the command code.
RAS#, CAS#, WE#
Input
Command Inputs: CAS#, RAS#, and WE# (along with CS#) define the command to be executed.
Bank Address Inputs: BA0 and BA1 select to which internal bank an ACTIVE, READ, WRITE, or
BA1, BA0
Input
PRECHARGE command is being applied. They also define which mode register (mode register or
4
extended mode register) is loaded during a MODE REGISTER SET command.
Address Inputs: During a Bank Activate command cycle, A0-A11 defines the row address (RA0-
RA11). During a Read or Write command cycle, A0-A7 defines the column address (CA0-CA7).
In addition to the column address, A8/AP is used to invoke autoprecharge operation at the end of the
burst read or write cycle. If A8 is high, the active bank is precharged. If A8 is low, the Autoprecharge
A11.. A0
Input
function is disabled.
During a Precharge command cycle, A8/AP is used to determine, which bank(s) will be precharged. If
A8/AP is high, all four banks will be precharged regardless of the state of BA0 and BA1. If A8/AP is low,
BA0 and BA1 define the bank to be precharged.
The address inputs also provide the op-code during a MODE REGISTER SET command.
Data Strobes: The DQSx are the bidirectional strobe signals. At read cycles, the DQSx signals are
generated by the SGRAM and are edge-aligned to the data. At write cycles, the DQS signals are
generated by the controller. The rising or falling edge indicates the center of the data valid window.
DQS3.. DQS0
I/O
Before and after a transfer cycle, DQSx enters a preamble and a postamble state. The DQSx signals
are mapped to the following data bytes: DQS0 to DQ0.. DQ7, DQS1 to DQ8.. DQ15, DQS2 to
DQ16..DQ23, DQS3 to DQ24.. DQ31.
Data Input/Output: The DQx signals form the 32 bit wide data bus. At READ cycles the pins are
DQ31.. DQ0
I/O
outputs and during WRITE cycles inputs. The data is transferred at both edges of the DQSx signals.
Input Data Mask: The DM signals are input mask signal for WRITE data. They mask off a complete
byte on the data bus. DMx = 1 prevents the corresponding byte from being written. DM3 corresponds
DM3.. DM0
Input
to DQ31..DQ24, DM2 to DQ23..DQ16, DM1 to DQ15..DQ8, DM0 to DQ7..DQ0. DM signals are
sampled on both edges of DQS.
Although DM pins are input-only, the DM loading is designed to match that of DQ and DQS pins.
V ref
Input
Voltage Reference: V ref is the reference voltage input signal.
Power Supply: Power and Ground for the internal logic.
V DD = 2.5V +/- 5% for L4.5, -4.5 and -5
V DD , V SS
Supply
2.5V -5% < VDD < 2.9V for L3.6 and -3.6
2.5V < VDD < 2.9V for -3.0 and -3.3
IO Power Supply: Isolated Power and Ground for the output buffers to provide improved noise
V DDQ , V SSQ
Supply
immunity. V DDQ = 2.5V +/- 5%
NC, RFU
-
Please do not connect No Connect, Reserved for Future Use pins.
MCL
-
Must be connected to low
Note: The "#" sign marks a signal as low active.
VGN-S36C/S36GP/S36LP/S36SP/S36TP/S38CP/S52B/
S62PS/S62PSY/S62S/S350F/S350FP/S360/S360P/S370F
1-13
5
6
7
8
9
10
DQ
DQ
DQ
DQ
V
DQ
3
2
0
31
28
SSQ
29
DQ
V
V
DQ
V
NC
1
DDQ
DDQ
30
DDQ
V
V
V
V
V
V
SSQ
DD
DD
SSQ
SSQ
SSQ
V
V
V
V
V
V
SSQ
SS
SS
SSQ
SS
DD
V
V
TOP VIEW
SSQ
DDQ
128 BALL XBGA
V
V
SSQ
DDQ
4 Banks x 4096 Rows
V
NC
SSQ
x 256 Columns x 32 Bits
V
V
SSQ
DDQ
V
V
V
V
V
V
SS
SS
SS
SS
SSQ
DDQ
A
V
V
V
V
RFU
10
DD
DD
SS
DD
A
A
CLK
A
A
RFU
1
2
11
9
5
A
A
A
A
A
A8/AP
1
3
4
6
7
Detailed Function
Confidential
IC
11
12
DM
DQS
3
3
V
DQ
DDQ
27
DQ
DQ
26
25
V
DQ
DDQ
24
DQ
DQ
15
14
DQ
DQ
13
12
DM
DQS
1
1
DQ
DQ
11
10
DQ
DQ
9
8
NC
NC
CLK#
MCL
V
CKE
REF
(J/AM/AO)
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