Table of Contents
Advertisement
ELECTRICAL CHARACTERISTICS (continued)
= SHDN = 5V, SKIP = GND, T
(V+ = 15V, V
= V
= -40°C to +85°C, unless otherwise noted.) (Note 4)
CC
DD
A
PARAMETER
SYMBOL
Minimum Off-Time
t
(Note 3)
OFF(MIN)
FB forced above the regulation point,
LSAT = GND
Quiescent Supply Current (V
)
I
CC
CC
FB forced above the regulation point,
V
> 0.5V
LSAT
Quiescent Supply Current (V
)
I
FB forced above the regulation point
DD
DD
Quiescent Supply Current (V+)
I
V+
SHDN = GND
Shutdown Supply Current (V
)
CC
SHDN = GND
Shutdown Supply Current (V
)
DD
SHDN = GND, V+ = 28V,
Shutdown Supply Current (V+)
V
= V
= 0 or 5V
CC
DD
REFERENCE
Reference Voltage
V
V
= 4.5V to 5.5V, I
REF
CC
REFIN Voltage Range
FAULT DETECTION
With respect to error comparator threshold,
Overvoltage Trip Threshold
OVP/UVP = V
Output Undervoltage Protection
With respect to error comparator threshold,
Trip Threshold
OVP/UVP = V
With respect to error comparator threshold,
PGOOD Lower Trip Threshold
hysteresis = 1%
With respect to error comparator threshold,
PGOOD Upper Trip Threshold
hysteresis = 1%
V
Undervoltage Lockout
Rising edge, PWM disabled below this level
CC
V
UVLO(VCC)
Threshold
hysteresis = 20mV
CURRENT LIMIT
CSP
Current-Limit Input Range
CSN
Valley Current-Limit Threshold
V
V
- V
, ILIM = V
LIM(VAL)
CSP
CSN
(Fixed)
Valley Current-Limit Threshold
V
V
- V
, V
LIM(VAL)
CSP
CSN
(Adjustable)
ELECTRICAL CHARACTERISTICS (continued)
= SHDN = 5V, SKIP = GND, T
(V+ = 15V, V
= V
= -40°C to +85°C, unless otherwise noted.) (Note 4)
CC
DD
A
PARAMETER
SYMBOL
INPUTS AND OUTPUTS
SHDN, SKIP, GATE
Logic Input Threshold
rising edge, hysteresis = 225mV
Dual Mode Threshold Voltage
MAX1992 FB
TON, OVP/UVP,
Four-Level Input Logic Levels
LSAT, FBLANK
Note 2: When the inductor is in continuous conduction, the output voltage has a DC regulation level higher than the error compara-
tor threshold by 50% of the output ripple. In discontinuous conduction ( SKIP = GND, light load), the output voltage has a
DC regulation level higher than the trip level by approximately 1.5% due to slope compensation.
Note 3: On-time and off-time specifications are measured from 50% point to 50% point at the DH pin with LX = GND, V
and a 250pF capacitor connected from DH to LX. Actual in-circuit times can differ due to MOSFET switching speeds.
Note 4: Specifications to -40 °C are guaranteed by design, not production tested.
PIN
NAME
MAX1992
MAX1993
On-Time Selection Control Input. This four-level logic input sets the K-factor value
used to determine the DH on-time (see the On-Time One-Shot section). Connect to
analog ground (AGND or GND), REF, V
following nominal switching frequencies:
1
1
TON
V
= 200kHz
CC
Open = 300kHz
REF = 450kHz
AGND = 600kHz
2, 7, 8
—
N.C.
No Connection. Not internally connected.
Fault Blanking Control Input. This four-level logic input enables or disables fault
blanking, and sets the minimum forced-PWM operation time (t
blanking is enabled, PGOOD, OVP protection, and UVP protection are blanked for the
selected time period after a transition is detected on GATE. Additionally, the controller
enters forced-PWM mode for the duration of t
—
2
FBLANK
Connect FBLANK as follows:
V
= 140µs (min) t
CC
Open = 90µs (min) t
REF = 40µs (min) t
AGND = 90µs (min) t
CONDITIONS
MIN
MAX
UNITS
500
0.85
1.0
5
40
7
5
5
= 0
1.980
2.020
REF
0.7
V
REF
10
20
CC
65
75
CC
-14
-6
+6
+14
4.1
4.4
0
2.7
-0.3
+28.0
35
65
CC
= 2.00V
160
240
ILIM
CONDITIONS
MIN
MAX
UNITS
1.20
2.20
High
1.9
2.1
Low
0.05
0.15
V
-
CC
High
0.4V
Open
3.15
3.85
REF
1.65
2.35
Low
0.5
= 5V,
BST
Pin Description
FUNCTION
, or leave TON unconnected to select the
CC
). When fault
FBLANK
anytime GATE changes states.
FBLANK
, fault blanking enabled
FBLANK
, fault blanking enabled
FBLANK
, fault blanking enabled
FBLANK
, fault blanking disabled
FBLANK
PIN
NAME
MAX1992
MAX1993
ns
mA
3
3
LSAT
µA
µA
µA
µA
µA
4
4
PGOOD
V
V
5
5
ILIM
%
%
%
6
6
REF
%
—
7
REFIN
V
—
8
OD
V
9
9
FB
mV
mV
10
10
OUT
11
11
CSP
V
PIN
NAME
MAX1992
MAX1993
V
12
12
CSN
V
SKIP
13
13
14
14
V+
15
15
DH
16
16
LX
17
17
BST
18
18
DL
19
19
V
DD
20
—
PGND
—
20
GND
21
—
AGND
—
21
GATE
22
22
V
CC
PIN
NAME
MAX1992
MAX1993
SHDN
23
23
24
24
OVP/UVP
VGN-S36C/S36GP/S36LP/S36SP/S36TP/S38CP/S52B/
S62PS/S62PSY/S62S/S350F/S350FP/S360/S360P/S370F
1-29
Pin Description (continued)
FUNCTION
Inductor Saturation Control Input. This four-level logic input sets the inductor current
saturation limit as a multiple of the valley current-limit threshold set by ILIM, or
disables the function if not required. Connect LSAT to the following pins to set the
saturation current limit:
= 2 × I
V
CC
LIM(VAL)
Open = 1.75 × I
LIM(VAL)
REF = 1.5 × I
LIM(VAL)
AGND = disable LSAT protection
See the Inductor Saturation Limit and Setting the Current Limit sections.
Open-Drain Power-Good Output. PGOOD is low when the output voltage is more than
10% (typ) above or below the normal regulation point, during soft-start, and in
shutdown. After the soft-start circuit has terminated, PGOOD becomes high
impedance if the output is in regulation. For the MAX1993, PGOOD is
blanked —forced high-impedance state —when FBLANK is enabled and the controller
detects a transition on GATE.
Valley Current-Limit Threshold Adjustment. The valley current-limit threshold defaults
to 50mV if ILIM is tied to V
. In adjustable mode, the valley current-limit threshold
CC
across CSP and CSN is precisely 1/10th the voltage seen at ILIM over a 250mV to
2.5V range. The logic threshold for switchover to the 50mV default value is
approximately V
- 1V. When the inductor saturation protection threshold is
CC
exceeded, ILIM sinks 6µA. See the Current-Limit Protection (ILIM) section.
2.0V Reference Voltage Output. Bypass REF to analog ground with a 0.1µF or greater
ceramic capacitor. The reference can source up to 50µA for external loads. Loading
REF degrades output voltage accuracy according to the REF load regulation error.
The reference is disabled when the MAX1992/MAX1993 is shut down.
External Reference Input. REFIN sets the feedback regulation voltage (V
of the MAX1993.
Open-Drain Output. Controlled by GATE.
Feedback Input.
MAX1992: Connect to V
for a +1.8V fixed output or to AGND for a +2.5V fixed
CC
output. For an adjustable output (0.7V to 5.5V), connect FB to a resistive divider from
the output voltage. The FB regulation level is +0.7V.
MAX1993: The FB regulation level is set by the voltage at REFIN.
Output Voltage Sense. Connect directly to the positive terminal of the output
capacitors as shown in the standard application circuits (Figures 1 and 9). OUT
senses the output voltage to determine the on-time for the high-side switching
MOSFET. For the MAX1992, OUT also serves as the feedback input when using the
preset internal output voltages as shown in Figure 7. When discharge mode is
enabled by OVP/UVP, the output capacitor is discharged through an internal 10 Ω
resistor connected between OUT and ground.
Positive Current-Sense Input. Connect to the positive terminal of the current-sense
element. Figure 10 and Table 7 describe several current-sensing options. The PWM
controller does not begin a cycle unless the current sensed is less than the valley
current-limit threshold programmed at ILIM.
Pin Description (continued)
FUNCTION
Negative Current-Sense Input. Connect to the negative terminal of the current-sense
element. Figure 10 and Table 7 describe several current-sensing options. The PWM
controller does not begin a cycle unless the current sensed is less than the valley
current-limit threshold programmed at ILIM.
Pulse-Skipping Control Input. Connect SKIP to V
for low-noise, forced-PWM mode
CC
or connect SKIP to analog ground (AGND or GND) to enable pulse-skipping
operation.
Battery Voltage-Sense Connection. The controller only uses V+ to set the on-time one-
shot timing. The DH on-time is inversely proportional to input voltage over a range of
2V to 28V.
High-Side Gate-Driver Output. DH swings from LX to BST.
Inductor Connection. Connect LX to the switched side of the inductor. LX serves as
the lower supply rail for the DH high-side gate driver.
Boost Flying Capacitor Connection. Connect to an external capacitor and diode as
shown in Figure 6. An optional resistor in series with BST allows the DH pullup current
to be adjusted.
Low-Side Gate-Driver Output. DL swings from PGND to V
(MAX1992) or GND to
DD
V
(MAX1993).
DD
Supply Voltage Input for the DL Gate Driver. Connect to the system supply voltage
(+4.5V to +5.5V). Bypass V
to PGND with a 1µF or greater ceramic capacitor.
DD
Power Ground. Ground connection for the DL low-side gate driver.
Analog and Power Ground. AGND and PGND connect together internally. Connect
backside pad to GND.
Analog Ground. Connect backside pad to AGND.
Buffered N-Channel MOSFET Gate Input. A logic low on GATE turns off the internal
MOSFET so OD appears as a high impedance. A logic high on GATE turns on the
internal MOSFET, pulling OD to ground.
Analog Supply Input. Connect to the system supply voltage (+4.5V to +5.5V) through
a series 20Ω resistor. Bypass V
to analog ground with a 1µF or greater ceramic
CC
capacitor.
Pin Description (continued)
FUNCTION
Shutdown Control Input. Connect to V
for normal operation. Connect to analog
CC
ground to put the controller into its 1µA shutdown state. When discharge mode is
enabled by OVP/UVP, the output is discharged through a 10 Ω resistor between OUT
and ground, and DL is forced high after V
drops below 0.3V. When discharge
OUT
mode is disabled by OVP/UVP, OUT remains a high-impedance input and DL is
forced low, so LX also appears as a high-impedance input. A rising edge on SHDN
clears the fault-protection latch.
Overvoltage/Undervoltage Protection and Discharge Mode Control Input. This four-
level logic input selects between various output fault-protection options (Table 6) by
selectively enabling OVP protection and UVP protection. When enabled, the OVP limit
defaults at 116% of the nominal output voltage, and the UVP limit defaults at 70% of
the nominal output voltage. Discharge mode is enabled when UVP protection is also
enabled. Connect OVP/UVP to the following pins for the desired function:
V
= enable OVP and discharge mode, enable UVP
CC
Open = enable OVP and discharge mode, disable UVP
REF = disable OVP and discharge mode, enable UVP
AGND = disable OVP and discharge mode, and UVP
See the Fault Protection and Shutdown and Output Discharge sections.
Confidential
(J/AM/AO)
IC
= V
)
FB
REFIN
Advertisement
Table of Contents
