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Electrical Characteristics
LM2724
VCC = BOOT = SYNC = 5V, SW = GND = 0V, unless otherwise specified. Typicals and limits appearing in plain type
apply for T
= T
= +25°C. Limits appearing in boldface type apply over the entire operating temperature range.
A
J
Symbol
Parameter
Conditions
POWER SUPPLY
I
Operating Quiescent Cur-
IN = 0V.
q_op
rent
TOP DRIVER
Peak Pull-up Current
Pull-up Rds_on
I
= I
= 0.7A
BOOT
HG
Peak Pull-down Current
Pull-down Rds_on
I
= I
= 0.7A
SW
HG
t
Rise Time
Timing Diagram, C
4
t
Fall Time
Timing Diagram, C
6
t
Pull-up Dead Time
Timing Diagram
3
Timing Diagram, IN ↓.
t
Pull-down Delay
5
BOTTOM DRIVER
Peak Pull-up Current
Pull-up Rds_on
I
= I
= 0.7A
VCC
LG
Peak Pull-down Current
Pull-down Rds_on
I
= I
= 0.7A
GND
LG
Electrical Characteristics (continued)
LM2724
VCC = BOOT = 5V, SW = GND = 0V, unless otherwise specified. Typicals and limits appearing in plain type apply for T
= T
= +25°C. Limits appearing in boldface type apply over the entire operating temperature range.
J
Symbol
Parameter
Conditions
t
Rise Time
Timing Diagram, C
8
t
Fall Time
Timing Diagram, C
2
t
Pull-up Dead Time
Timing Diagram
7
t
Pull-down Delay
Timing Diagram
1
LOGIC
V
VCC Under-Voltage-Lock-
VCC rises from 0V toward 5V
uvlo_up
Out Upper Threshold
V
VCC Under-Voltage-Lock-
VCC falls from 5V toward 0V
uvlo_dn
Out Lower Threshold
V
VCC Under-Voltage-Lock-
VCC falls from 5V toward 0V
uvlo_hys
Out Hysteresis
V
SYNC Pin High Input
IH_SYNC
V
SYNC Pin Low Input
IL_SYNC
I
SYNC = 5V, sink current
leak_SYNC
SYNC Pin Leakage Cur-
rent
SYNC = 0V, source current
IN = 5V, sink current
I
IN Pin Leakage Current
leak_IN
IN = 0V, source current
t
Minimum Positive Output
on_min
Pulse Width (Note 4)
t
Minimum Negative Output
off_min
Pulse Width (Note 5)
t
Minimum Pulse Width at
IN_min
the IN Pin
V
IN High Level Input Volt-
When IN pin goes high from 0V
IH_IN
age
V
IN Low Level Input Volt-
When IN pin goes low from 5V
IL_IN
age
Note 1: Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating ratings are
conditions under which the device operates correctly. Operating Ratings do not imply guaranteed performance limits.
Note 2: Maximum allowable power dissipation is a function of the maximum junction temperature, T
ambient thermal resistance, θ
, and the ambient temperature, T
JA
ambient temperature is calculated using: P
=(T
-T
MAX
JMAX
A
LM2724 SO-8 package is 172°C/W. For a T
of 150°C and T
JMAX
0.7W. The θ
for the LM2724 LLP-8 package is 39°C/W. For a T
JA
power dissipation is 3.2W.
Note 3: ESD machine model susceptibility is 200V.
Note 4: Whenever the LM2724 sees a rising edge at the IN pin after IN has been low for at least t
driver will be turned on for at least t
. Otherwise the edge will be ignored.
on_min
Note 5: Whenever the LM2724 sees a falling edge at the IN pin after IN has been high for at least t
driver will be turned on for at least t
. Otherwise the edge will be ignored.
off_min
Note 6: At the IN pin, if a falling edge is followed by a rising edge within 5ns, the HG may ignore the rising edge and re-
main low until the IN pin toggles again. If a rising edge is followed by a falling edge within 5ns, the pulse may be com-
pletely ignored.
Min
Typ
Max
Units
142
195
3.0
1.2
-3.2
0.5
= 3.3nF
17
LOAD
= 3.3nF
12
LOAD
19
27
3.2
1.1
3.2
0.6
Min
Typ
Max
Units
= 3.3nF
17
LOAD
= 3.3nF
14
LOAD
22
13
4
2.5
0.8
55%
VCC
25%
2
10
10
2
50
50
5
55%
VCC
25%
, the junction-to-
JMAX
. The maximum allowable power dissipation at any
A
θ
. The junction-to-ambient thermal resistance, θ
) /
, for the
JA
JA
of 25°C, the maximum allowable power dissipation is
A
of 150°C and T
of 25°C, the maximum allowable
JMAX
A
, the high-side
off_min
, the low-side
on_min
Block Diagram
+4V ~ +7V
VCC
µA
Power
VCC
On
Reset
A
SYNC
Logic
Ω
IN
A
Ω
Shoot-through
ns
Protection
ns
ns
Pin Description
ns
Pin #
Pin Name
Pin Function
1
SW
Top driver return. Should be connected to the common node of top and bottom FETs.
2
HG
Top gate drive output. Should be connected to the top FET gate.
A
3
BOOT
Bootstrap. Accepts a bootstrap voltage for powering the high-side driver.
Ω
4
IN
Accepts a logic control signal.
5
SYNC
Bottom gate enable.
A
6
VCC
Connect to +5V supply.
Ω
7
LG
Bottom gate drive output. Should be connected to bottom FET gate.
8
GND
Ground.
A
ns
ns
ns
ns
V
V
V
µA
µA
ns
ns
ns
VGN-S36C/S36GP/S36LP/S36SP/S36TP/S38CP/S52B/
S62PS/S62PSY/S62S/S350F/S350FP/S360/S360P/S370F
1-18
IC
BOOT
VIN (up to 33V)
HG
Q
1
SW
+
VOUT
-
Q
2
LG
Items in bold
are external
to the IC.
GND
Confidential
(J/AM/AO)
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