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If the TLC694x device detects three SCLK rising edges during the LAT-signal high period, it considers this
as a vertical frame synchronization command (VSYNC) command
initialized once the VSYNC command is received.
NUMBER OF SCLK RISING
COMMAND NAME
VSYNC
Send VSYNC Command:
GS
GS
SIN
Bit 15
Bit 14
SCLK
1
2
LAT
BANK_SEL
BANK_SEL = 0 (or 1)
(Internal bit)
Line Counter
Old Line Counter Value
(Internal bit)
Channel Counter
Old Channel Counter Value
(Internal bit)
GS Counter
Old GS Counter Value
(Internal bit)
Line Read Counter
Old Line Read Counter value
(Internal bit)
Sub-period Counter
Old Sub-period Counter Value
(Internal bit)
3.2.2 Send VSYNC Command
After all the grayscale (GS) data is written into the selected memory BANK, the external controller sends
the VSYNC command to the TLC694x device. When the VSYNC command is received, the grayscale
data of the memory BANK selected in the previous step is displayed in the coming frame period.
3.3
PWM Control and New Frame Image Display
3.3.1 PWM Control Overview
PWM control means the pulse-width modulation (PWM) control scheme, which controls the turnon ratio of
the output channel OUTn during one display period. The turnon ratio is proportional to the grayscale (GS)
data of this channel. The use of 16-bit GS data per channel results in 65,536 brightness steps, from 0%
up to 100% brightness.
For example:
•
If GS = 0, then OUTn does not turn on during one display period (65,536 GCLK periods, total), and the
brightness ratio is 0%.
•
If GS = 255 (00FFh), then during one display period, OUTn turns on for 255 GCLK periods, and the
brightness ratio is 255 / 65 535 = 0.3891% (Assume 100% brightness if OUTn turns on for 65 535
GCLK periods during one display period).
SLVUBF4A – February 2018 – Revised June 2019
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TI Information — Selective Disclosure
Table 3-2. VSYNC Command Description
EDGES WHEN LAT IS
HIGH
Vertical frame synchronization command. When this command is received,
3
BANK_SEL toggles, and all internal counters are reset to 0. A new frame
image is displayed in the coming frame period.
GS
GS
GS
Bit 13
Bit 2
Bit 1
3
14
15
WRTGS
Figure 3-5. Send VSYNC Command
Copyright © 2018–2019, Texas Instruments Incorporated
Vertical Frame Synchronization (VSYNC)
(Table
Figure 3-5
shows the VSYNC command timing diagram.
DESCRIPTION
GS
Bit 0
16
1
VSYNC
Old Channel Counter Value Increased 1
3-2). All the internal counters are
2
3
BANK_SEL is toggled
Toggled to 1 (or 0)
All Counters are reset to 0
Reset to 0
Reset to 0
Reset to 0
Reset to 0
Reset to 0
PWM Grayscale Control
31
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