Related Manuals for Texas Instruments TLC5540
Summary of Contents for Texas Instruments TLC5540
- Page 1 TLC5540/TLC5510/TLC5510A/ TL V5540/TL V5510 Evaluation Module User’s Guide 1999 Mixed-Signal Products SLAU007C...
- Page 2 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability.
- Page 3 Read This First About This Manual The purpose of this user’s guide is to serve as a reference book for the TLC5540/TLC5510/TLC5510A/TLV5510/TLV5540 devices. This document provides information to assist managers and hardware / software engineers in application development. How to Use This Manual...
- Page 4 Related Documentation From Texas Instruments Related Documentation From Texas Instruments The following documents may be ordered by contacting the Texas Instruments Product Information Center at one of the numbers listed on the next page, or, they may be downloaded at: http://www–s.ti.com/sc/docs/psheets/pids2.htm...
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Page 5: Table Of Contents
Running Title—Attribute Reference Contents Overview ............... . Purpose . - Page 6 Running Title—Attribute Reference Figures 2–1 Board Schematic ............. . 3–1 EVM Board Layout .
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Page 7: Overview
Chapter 1 Overview This chapter gives an overview of the TLC5540/TLC5510/TLC5510A/ TLV5540/TLV5510 evaluation module (EVM). Topic Page Power Supply Requirements ........ -
Page 8: Purpose
Purpose 1.1 Purpose The TLC5540/TLC5510/TLC5510A/TLV5540/TLV5510 evaluation module (EVM) provides a platform for lab prototype evaluation of the Texas Instru- ments TLC5540/TLC5510/TLC5510A/TLV5540/TLV5510 8-bit, high-speed analog-to-digital converters. Since practical operation can be acheived in excess of 40 MHz, the circuit layout is critical and does not lend itself to classic breadboarding techniques. -
Page 9: Power Supply Requirements
Power Supply Requirements 1.2 Power Supply Requirements The TLC5540/TLC5510/TLC5510A/TLV5540/TLV5510 EVM is designed to be powered by regulated lab power supplies. Three lab supplies are required for the best performance. Table 1–1. Power Supplies If Amp Used By-pass Amp TLC5540/5510/ TLC5510/... - Page 10 Overview...
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Page 11: Circuit Description
Chapter 2 Circuit Description This chapter describes the EVM circuit and its operation. Topic Page EVM Analog Input ..........2–2 Digital Output . -
Page 12: Evm Analog Input
Jumper J6 bypasses one of the internal bias resistors and thus alters the input bias range required by the input signal. With J6 installed, the voltage range of the TLC5540/TLC5510 is 0 V – 2.28 V and TLV5540/TLV5510 is 0 V – 2.74 V (at 3.3 V The TLC5510A uses only the center internal bias resistor with an externally- applied regulated 4-V reference to generate the device reference voltage. -
Page 13: Amplifier Input, Dc Coupled
Resistor R7 also provides isolation against a direct capacitive load (such as a scope probe) on the test point terminal. The amplifier output circuit is connected to the TLC5540/TLC5510/ TLC5510A/TLV5540/TLV5510 by soldering a jumper between terminals E10 and E12. -
Page 14: Input Bias Operational Range
0 V to 4 V (J11 and J16 Installed 0 V to 2.28 V 0 V to 2.74 V installed) Other output ranges can be configured. See the TLC5540/TLC5510/ TLC5510A/TLV5540/TLV5510 data sheets. 2.1.5 Test Points Test points TP1 and TP2 provide an oscilloscope connection to monitor the output of the analog input conditioning amplifier stage as follows: Table 2–3. -
Page 15: Digital Output
Digital Output 2.2 Digital Output An octal high-speed latch (U4) provides buffered digital data. The factory con- figuration uses this latch as a buffer to drive the 22-ohm line damping resistors. Pin 24 on the output connector (J5) can be used to drive the U4 output to a high impedance (3-state) allowing a bus interface to external circuitry. -
Page 16: Clock Circuit
DSP or microcontroller, resistor R1 should be removed from the circuit. The clock is buffered by inverters (U1) and provides a true (noninverted) output to the TLC5540/TLC5510/TLC5510A/TLV5540/TLV5510 and a true equivalent output at pin 22 of the output connector J5. This provides the user a buffered reference clock output for external circuitry. -
Page 17: Board Schematic
Board Schematic 2.4 Board Schematic Figure 2–1 shows the EVM board schematic. Circuit Description... -
Page 18: Board Schematic
Board Schematic... -
Page 19: Physical Description
Chapter 3 Physical Description This chapter describes the physical characteristics and PCB layout of the EVM and lists the components used on the module. Topic Page Board Layout ..........3–2 Board Layers . -
Page 20: Evm Board Layout
Board Layout 3.1 Board Layout Figure 3–1 shows the EVM board layout. Figure 3–1. EVM Board Layout Physical Description... -
Page 21: Evm Board Layer
Board Layers 3.2 Board Layers Figures 3–2 through 3–5 show the EVM board layers. Figure 3–2. EVM Board Layer 1 Physical Description... -
Page 22: Evm Board Layer
Board Layers Figure 3–3. EVM Board Layer 2 Physical Description... -
Page 23: Evm Board Layer
Board Layers Figure 3–4. EVM Board Layer 3 Physical Description... -
Page 24: Evm Board Layer
Board Layers Figure 3–5. EVM Board Layer 4 Physical Description... -
Page 25: Part Descriptions
C1, C3, C6, C8–C10, C12, C18, C19, C21, C22, C24, C27 † 68 pF capacitor, 50 V, 5%, NPO, SMD, size 1210 100 pF (TLC5540)/150 pF(TLC5510/TLC5510A) capacitor, 50 V, 5%, NPO, SMD, size 0805 † FB1–FB5 Ferrite bead, SMD, size 1206, Murata BLM31B601SPT Connector, BNC, 50 Ω, vertical, PC mount...