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Board Layout
3 Board Layout
This section provides a description of the TPS54233EVM-373, board layout, and layer illustrations.
3.1 Layout
The board layout for the TPS54233EVM-373 is shown in
EVM is laid out in a manner typical of a user application. The top and bottom layers are 2-oz. copper.
The top layer contains the main power traces for V
for the remaining pins of the TPS54233 and a large area filled with ground. The bottom layer contains ground
and a signal route for the BOOT capacitor. The top and bottom and internal ground traces are connected with
multiple vias placed around the board including ten vias directly under the TPS54233 device to provide a thermal
path from the top-side ground plane to the bottom-side ground plane.
The input decoupling capacitors (C1, C2, and C3) and bootstrap capacitor (C4) are all located as close to the
IC as possible. In addition, the voltage set-point resistor divider components are also kept close to the IC. The
voltage divider network ties to the output voltage at the point of regulation, the copper V
capacitor C9. For the TPS54233, an additional input bulk capacitor may be required, depending on the EVM
connection to the input supply.
10
TPS54233 Step-Down Converter Evaluation Module User's Guide
, V
IN
OUT
Figure 3-1. TPS54233EVM-373 Top-Side Layout
Copyright © 2021 Texas Instruments Incorporated
Figure 3-1
through
Figure
, and VPHASE. Also on the top layer are connections
SLVU264A – NOVEMBER 2008 – REVISED OCTOBER 2021
www.ti.com
3-3. The topside layer of the
trace past the output
OUT
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