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4.3
Voltage Mode
100
V
= 4.2 V
IN
90
80
70
60
50
40
30
20
10
0
1
10
Figure 8. Efficiency vs Input Voltage
5
BOARD LAYOUT
Proper board layout is important for all high-frequency switch-mode power supplies.
Figure 14
show the board layout for the TPS61310EVM-638 PCB. The nodes with high switching
frequencies and currents are kept as short as possible to minimize trace inductance. Careful attention has
been given to the routing of high-frequency current loops. A single-point grounding scheme is used. Also,
the majority of the heat sinking for this device occurs through the top layer traces and vias pulled from the
IC's solder bumps that carry high currents. For specific layout guidelines, see the
SLVU419 – April 2011
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V
= 3.6 V
IN
V
= 2.5 V
IN
V
= 3 V
IN
PFM/PWM Operation
Forced PWM Operation
V
= 4.95 V
OUT
I
= 1750 mA
LIM
Voltage Mode Regulation
100
1000
I - Output Current - mA
O
Figure 10. Assembly Layer
Copyright © 2011, Texas Instruments Incorporated
V = 3.6V,
V
IN
OUT
I
= 1750mA
LIM
50mA to 500mA Load Step
I
OUT
(500mA/div)
10000
Figure 9. Load Transient
TPS61310EVM-638 Evaluation Module User Guide
BOARD LAYOUT
= 4.95V
V
OUT
(500mV/div - 4.95V Offset)
I
L
(500mA/div)
PFM/PWM Operation
ENPSM bit = 1
t - Time = 50 s/div
m
Figure 10
through
TPS61310 data
sheet.
7
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