Epson S1C17624 Technical Manual page 87

Attempting a write or stop operation may corrupt the counter values if 1 is being carried over. There-
fore, this bit should be checked to confirm that the counters are not in a carry (busy) state before writing
data to the counter registers.
When a value of 0 is read from RTCBSY after writing 1 to RTCHLD, it means that carry is not taking
place. In this state, counter data can be written to.
After 1 is written to RTCHLD, the counters stop operating. So RTCBSY is fixed at 0, as carry will not
take place. In this case, the counter hold function is also actuated, with a carry over of 1 to the 1-second
counter disabled in hardware. The divider (counter for less than one second) continues operating.
Write data to the counter registers. After writing data, reset RTCHLD to 0.
If 1 is being carried over when data is being written to a counter in the hold state, 1 second is automati-
cally added to correct the counter values when RTCHLD is reset to 0. This correction is only effective
for 1 second and no correction is conducted on the carry encountered in the second time and on. In this
case, the timekeeping data gets out of order. Therefore, be sure to reset RTCHLD to 0 as soon as pos-
sible after completing the required write operation.
When a value of 1 is read from RTCBSY after writing 1 to RTCHLD, it means that carry is taking
place. In this case, writing 1 to RTCHLD is ignored and RTCHLD retains 0. A period of 4 ms per
second is required for a carry over of 1 to the counters. In this case, repeat writing 1 to RTCHLD and
checking RTCBSY, or write 1 to RTCHLD and check RTCBSY after waiting for 4 ms.
D0 RTChlD: Counter hold Control Bit
This bit allows the busy state of counters to be checked and the counters held intact.
1 (R/W): Checks for busy state/Holds counters
0 (R/W): Normal operation (software reset value)
For the operation of this bit, see the description of RTCBSY above.
RTC Second Register (RTC_SeC)
Register name address Bit
RTC Second 0x5144
D7
Register (8 bits)
D6–4 RTCSh[2:0] RTC 10-second counter
(RTC_SeC)
D3–0 RTCSl[3:0] RTC 1-second counter
* Software reset (RTCRST → 1 → 0) does not affect the counter values. This register retains the value set before a software reset is
performed.
note: Data should not be read from or written to the counters while 1 is being carried over. (See Section
8.3.5, "Counter Hold and Busy Flag," and Section 8.3.7, "Counter Read.")
D7 Reserved
D[6:4] RTCSh[2:0]: RTC 10-second Counter Bits
These bits comprise a 3-bit BCD counter used to count tens of seconds.
The counter counts from 0 to 5 with a carry over of 1 from the 1-second counter. This counter is reset to
0 after 5 and outputs a carry over of 1 to the 1-minute counter.
D[3:0] RTCSl[3:0]: RTC 1-second Counter Bits
These bits comprise a 4-bit BCD counter used to count units of seconds.
The counter counts from 0 to 9 synchronously with a 1-second signal derived from the 32.768-kHz
OSC1 clock. This counter is reset to 0 after 9 and outputs a carry over of 1 to the 10-second counter.
RTC Minute Register (RTC_Min)
Register name address Bit
RTC Minute 0x5145 D7
Register
(8 bits) D6–4 RTCMih[2:0] RTC 10-minute counter
(RTC_Min)
D3–0 RTCMil[3:0] RTC 1-minute counter
* Software reset (RTCRST → 1 → 0) does not affect the counter values. This register retains the value set before a software reset is
performed.
note: Data should not be read from or written to the counters while 1 is being carried over. (See Section
8.3.5, "Counter Hold and Busy Flag," and Section 8.3.7, "Counter Read.")
S1C17624/604/622/602/621 TeChniCal Manual
name Function
–
reserved
name Function
– reserved
Seiko epson Corporation
8 Real-TiMe ClOCK (RTC)
Setting init. R/W
– – – 0 when being read.
0 to 5 X (*) R/W
0 to 9 X (*) R/W
Setting init. R/W
– – – 0 when being read.
0 to 5 X (*) R/W
0 to 9 X (*) R/W
Remarks
Remarks
8-13