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0x4360–0x436c
Register name address
Bit
2
i
C Slave
0x4360
D15–8 –
Transmit Data
D7–0 SDaTa[7:0] I
(16 bits)
Register
(i2CS_TRnS)
i
2
C Slave
0x4362
D15–8 –
Receive Data
D7–0 RDaTa[7:0] I
(16 bits)
Register
(i2CS_ReCV)
i
2
C Slave
0x4364
D15–7 –
address Setup
(16 bits)
D6–0 SaDRS[6:0] I
Register
(i2CS_SaDRS)
i
2
C Slave
0x4366
D15–9 –
Control Register
(16 bits)
D8
(i2CS_CTl)
D7
D6
D5
D4
D3
D2
D1
D0
i
2
C Slave
0x4368
D15–8 –
Status Register
(16 bits)
D7
(i2CS_STaT)
D6
D5
D4
D3
D2
D1
D0
2
i
C Slave
0x436a
D15–5 –
access Status
(16 bits)
D4
Register
D3
(i2CS_aSTaT)
D2
D1
D0
i
2
C Slave
0x436c
D15–3 –
interrupt Control
(16 bits)
D2
Register
D1
(i2CS_iCTl)
D0
0x5000–0x5003
Register name address
Bit
Clock Timer
0x5000
D7–5 –
Control Register
(8 bits)
D4
(CT_CTl)
D3–1 –
D0
Clock Timer
0x5001
D7–0 CTCnT[7:0] Clock timer counter value
Counter Register
(8 bits)
(CT_CnT)
Clock Timer
0x5002
D7–4 –
interrupt Mask
(8 bits)
D3
Register
D2
(CT_iMSK)
D1
D0
Clock Timer
0x5003
D7–4 –
interrupt Flag
(8 bits)
D3
Register
D2
(CT_iFlG)
D1
D0
0x5020–0x5023
Register name address
Bit
Stopwatch
0x5020
D7–5 –
Timer Control
(8 bits)
D4
Register
D3–1 –
(SWT_CTl)
D0
S1C17624/604/622/602/621 TeChniCal Manual
name
Function
reserved
2
C slave transmit data
reserved
2
C slave receive data
reserved
2
C slave address
reserved
TBuF_ClR I2CS_TRNS register clear
i2CSen
I
2
C slave enable
SOFTReSeT Software reset
naK_anS
NAK answer
BFReQ_en Bus free request enable
ClKSTR_en Clock stretch On/Off
nF_en
Noise filter On/Off
aSDeT_en Async.address detection On/Off
COM_MODe I
2
C slave communication mode
reserved
BSTaT
Bus status transition
–
reserved
TXuDF
Transmit data underflow
RXOVF
Receive data overflow
BFReQ
Bus free request
DMS
Output data mismatch
aSDeT
Async. address detection status
Da_naK
NAK receive status
Da_STOP
STOP condition detect
reserved
RXRDY
Receive data ready
TXeMP
Transmit data empty
BuSY
I
2
C bus status
SeleCTeD I
2
C slave select status
R/W
Read/write direction
reserved
BSTaT_ien Bus status interrupt enable
RXRDY_ien Receive interrupt enable
TXeMP_ien Transmit interrupt enable
name
Function
reserved
CTRST
Clock timer reset
reserved
CTRun
Clock timer run/stop control
reserved
CTie32
32 Hz interrupt enable
CTie8
8 Hz interrupt enable
CTie2
2 Hz interrupt enable
CTie1
1 Hz interrupt enable
reserved
CTiF32
32 Hz interrupt flag
CTiF8
8 Hz interrupt flag
CTiF2
2 Hz interrupt flag
CTiF1
1 Hz interrupt flag
name
Function
reserved
SWTRST
Stopwatch timer reset
reserved
SWTRun
Stopwatch timer run/stop control
Seiko epson Corporation
aPPenDiX a liST OF i/O ReGiSTeRS
Setting
init. R/W
–
0–0xff
0x0 R/W
–
0–0xff
0x0
–
0–0x7f
0x0 R/W
–
1 Clear state
0 Normal
1 Enable
0 Disable
1 Reset
0 Cancel
1 NAK
0 ACK
1 Enable
0 Disable
1 On
0 Off
1 On
0 Off
1 On
0 Off
1 Active
0 Standby
–
1 Changed
0 Unchanged
–
1 Occurred
0 Not occurred
1 Occurred
0 Not occurred
1 Error
0 Normal
1 Detected
0 Not detected
1 NAK
0 ACK
1 Detected
0 Not detected
–
1 Ready
0 Not ready
1 Empty
0 Not empty
1 Busy
0 Free
1 Selected
0 Not selected
1 Output
0 Input
–
1 Enable
0 Disable
1 Enable
0 Disable
1 Enable
0 Disable
Setting
init. R/W
–
1 Reset
0 Ignored
–
1 Run
0 Stop
0x0 to 0xff
–
1 Enable
0 Disable
1 Enable
0 Disable
1 Enable
0 Disable
1 Enable
0 Disable
–
1 Cause of
0 Cause of
interrupt
interrupt not
occurred
occurred
Setting
init. R/W
–
1 Reset
0 Ignored
–
1 Run
0 Stop
i
2
C Slave
Remarks
–
–
0 when being read.
–
–
0 when being read.
R
–
–
0 when being read.
–
–
0 when being read.
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
–
–
0 when being read.
0
R
–
–
0 when being read.
0
R/W Reset by writing 1.
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
–
–
0 when being read.
0
R
0
R
0
R
0
R
0
R
–
–
0 when being read.
0
R/W
0
R/W
0
R/W
Clock Timer
Remarks
–
–
0 when being read.
0
W
–
–
0
R/W
0
R
–
–
0 when being read.
0
R/W
0
R/W
0
R/W
0
R/W
–
–
0 when being read.
0
R/W Reset by writing 1.
0
R/W
0
R/W
0
R/W
Stopwatch Timer
Remarks
–
–
0 when being read.
0
W
–
–
0
R/W
aP-a-11
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