Epson S1C17624 Technical Manual page 267

Cmos 16-bit single chip microcontroller
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24 a/D COnVeRTeR (aDC10)
24.4.3
Reading a/D Conversion Results
Upon completion of the A/D conversion in the start channel, the A/D converter loads the conversion results into
ADD[15:0]/ADC10_ADD register and sets the conversion completion flag ADCF/ADC10_CTL register. If mul-
tiple channels are specified using ADCS[2:0]/ADC10_TRG register and ADCE[2:0]/ADC10_TRG register, the A/
D converter continues A/D conversions in the subsequent channels.
The results of A/D conversion are stored in ADD[15:0] each time conversion in one channel is completed. At the
same time, a conversion completion interrupt can be generated, enabling to read out the converted data. If no con-
version completion interrupt is used, read the conversion results from ADD[15:0] after confirming that ADCF is set
to 1 indicating completion of conversion. ADCF is reset to 0 when ADD[15:0] is read.
When a single channel or multiple channels are being converted continuously, the conversion results must be read
out from ADD[15:0] before the following conversion has completed. If the A/D conversion currently underway is
completed while ADCF is set to 1 (before reading the previous conversion results), ADD[15:0] is overwritten and
the overwrite error flag ADOWE/ADC10_CTL register is set to 1. At this time, a conversion data overwrite error
interrupt can be generated. After the conversion results are read from ADD[15:0], ADOWE should be read to check
whether the read data is valid or not. Or enable conversion data overwrite error interrupts and perform error han-
dling using the interrupt. Once ADOWE is set, it will not be reset until software writes 1. Since ADCF is also set
simultaneously with ADOWE, read out the converted data to reset ADCF.
note: Occurrence of an overwrite error does not stop continuous conversion.
24.4.4
Terminating a/D Conversion
One-time conversion mode (aDMS = 0)
In one-time mode, the A/D converter performs A/D conversion within the channel range successively beginning
with the conversion start channel specified by ADCS[2:0]/ADC10_TRG register and terminates once the con-
version end channel specified by ADCE[2:0]/ADC10_TRG register has been completed. ADCTL/ADC10_CTL
register is reset to 0 upon completion of the conversion sequence.
Continuous conversion mode (aDMS = 1)
In continuous conversion mode, the A/D converter repeatedly performs A/D conversion from the conversion
start channel to the conversion end channel. The hardware does not stop the conversion sequence. To stop A/D
conversion, write 0 to ADCTL. Since the conversion sequence is forcibly terminated, the results of the conver-
sion then underway cannot be obtained. ADEN/ADC10_CTL register must be set to 0 after a forced termina-
tion.
24.4.5
Timing Charts
Figure 24.4.5.1 shows the operations of the A/D converter.
ADEN
Trigger
ADIBS
A/D operation
ADD[15:0]
ADCF
Conversion result read
ADOWE
Interrupt request
(1) Single channel (AIN0) one-time conversion mode (ADCS = 0, ADCE = 0, ADMS = 0)
24-6
Ch.0
Sampling
Conversion
AIN0
AIN0
AIN0 converted data
Clear
Seiko epson Corporation
S1C17624/604/622/602/621 TeChniCal Manual

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