Epson S1C17624 Technical Manual page 82

8 Real-TiMe ClOCK (RTC)
8.4 RTC interrupts
The RTC has a function to generate interrupts at given intervals.
Since the RTC is active even in standby mode, interrupts may be used to cancel SLEEP mode.
This section describes the internal interrupt control function of the RTC. To generate interrupts to the CPU, the in-
terrupt controller (ITC) must also be set up. For details on how to control the ITC, see the "Interrupt Controller (ITC)"
chapter.
interrupt cycle setting
The interrupt cycle (in which the RTC outputs interrupt requests at specific intervals) can be selected from
seven choices listed in Table 8.4.1 by using RTCT[2:0]/RTC_INTMODE register.
RTCT[2:0] should be set while RTC interrupts are disabled. (See the procedure for enabling and disabling inter-
rupts described below.)
note: The system clock frequency must be set to 10 kHz or higher to use 1/512-second edge interrupts.
Setting interrupt conditions
The interrupt requests sent to the ITC can be selected as edge-triggered or level-sensed interrupts by setting a
register bit. RTCIMD/RTC_INTMODE register is the bit provided for this purpose.
Setting RTCIMD to 1 selects a level-sensed interrupt; setting it to 0 selects an edge-triggered interrupt.
When an edge-triggered interrupt has been selected, the RTC outputs an interrupt pulse to the ITC using the bus
clock supplied from the CLG. If a cause of interrupt occurs when the bus clock has not been supplied such as
in SLEEP mode, the RTC switches the interrupt mode to level-sensed and sets the interrupt signal to the active
level from occurrence of the interrupt cause until the bus clock supply is started.
enabling and disabling interrupts
The RTC interrupt requests output to the ITC are enabled by setting RTCIEN/RTC_INTMODE register to 1
and disabled by setting it to 0.
RTC interrupts will be generated according to the divider and counter status and the time between writing 1 to
RTCIEN and the first interrupt request is not fixed. Use the second and subsequent interrupts as valid.
interrupt status
When the RTC is up and running, RTCIRQ/RTC_INTSTAT register is set at the cyclic interrupt intervals set up
by RTCT[2:0]. When RTC interrupts are enabled by RTCIEN, interrupt requests are sent to the ITC.
Writing 1 to this status bit clears the bit. Because this bit is not cleared in hardware, be sure to clear it in soft-
ware after an interrupt is generated. If this bit remains set while interrupts are re-enabled or control is returned
from the interrupt handler routine by the reti instruction, the same interrupt may be generated again.
When RTCIEN is set to 0 (interrupt disabled), RTCIRQ is fixed at 0 (will not be set to 1).
Precautions
All RTC interrupt control bits described above are indeterminate when power is turned on. Moreover, these bits
are not initialized to specific values by an initial reset.
After power-on, an RTC interrupt request is masked (not output) regardless of the RTCIEN and RTCIRQ
settings until the clock supply to the RTC is enabled using RTCCE/RTC_CC register. However, be sure to set
RTCIEN to 0 (interrupt disabled) to prevent the occurrence of unwanted RTC interrupts.
8-8
Table 8. 4.1 Interrupt Cycle Settings
RTCT[2:0]
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
Seiko epson Corporation
interrupt cycle
Reserved
1/128 second
1/256 second
1/512 second
1 hour
1 minute
1 second
1/64 second
S1C17624/604/622/602/621 TeChniCal Manual