Chipset Features Setup - Lanner electronics FW-7650 Series User Manual

3.5 Chipset Features Setup

DRAM Clock :
the host clock and DIMM clock.
Host CLK (default)
66MHz
SDRAM Cycle Length : This item allows you to select the SDRAM cycle length. The
settings are 2 or 3.
CAS latency Time:
cycles of CAS latency depends on the DRAM timing. Do not reset this field from the
default value specified by the system designer.
DRAM RAS# to CAS# Delay:
The chipset support synchronous and asynchronous mode between
DIMM clock equal to host clock
DIMM clock equal to 66MHz
When synchronous DRAM is installed, the number of clock
This field lets you insert a timing delay