Hitachi 46W500 Training page 34

DP-3X SERIES CHASSIS MICROPROCESSOR NTSC SYNC INPUT CIRCUIT DIAGRAM
U301 Main Tuner 18
U302 Sub Tuner 18
7
UD2002
Digital Module
5
Front Control PWB
Aux 5 Video V3V
V5
Aux 5 S-Y V3Y
S5
Aux 5 S-C V3C
S-5 Det.
Aux 3 Video
V3
Aux 3 S-Y
S3
Aux 3 S-C
S-3 Det.
Aux 4 Video
V4
Aux 4 S-Y
S4 Aux 4 S-C
S-4 Det.
Input 2
Composite 2
Input 1
480i Only
PST1
TV
IV01
50 63
V6
Main Y
45 60
/Video
DM Y
31 3 Y1
32 5
C1
Sub Y
DM C
/Video
PFT
V4
2 22
Y4
7 24
C4
9 26
S-4
11 28
Selector IC
V3
15
Y3
17
C3
19
S-3
21
V2
8
Y2
10
Input 2
C2
12
Composite
S-2
V5 In
14
QV01 QV02
Terminal PWB
QV13 Q012
41
44
QV18
Q014
56 39
37
Q016
Y In (480i)
PiP Video and Sub
Video
are the same.
For 480i
Y Component
480i
Only for CCD
& V Chip
NTSC Only
IX02
30
Q041
Q035
SIGNAL PWB 1 of 2
I008
9
Main
Hi
3
Q010 Q009
Z
4
Sub
5
Q007
Lo
10
480i
Hi
1
Y
15
Sub
2
Q006
Lo
11
480i
Hi
13
Q003
X1
14
Main
12
Lo
16
SW +9V
I001
73
Main CCD Sel
74
Sub CCD Sel
25
SD Sel
Main CCD Infor
CCD & V Chip
100
Main CCD In
97
Sub CCD In
M/S Sync
Q025 23
Det
62
HBlk
Sub CCD In for
Q026
V. Chip Data
64
VBlk
Q042
M/S Sync Det.
93
Main AFC
(Main/Sub)
Q036
Used for AFC
during Channel
92
Sub AFC
tuning and Auto
Programming
Micro
Processor
Q005
Q008
Q004