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PCB Layout Guideline
The switching node rise and fall times must be minimized for minimum switching loss. Proper layout of the
components to minimize high-frequency current path loop is important to prevent electrical and magnetic
field radiation and high-frequency resonant problems. A printed-circuit board (PCB) layout priority list for
proper layout follows. Lay out the PCB according to this specific order is essential.
1. Place the input capacitor as close as possible to the switching MOSFET's supply and ground
connections, and use the shortest copper trace connection. These parts must be placed on the same
PCB layer instead of on different layers, and use vias to make this connection.
2. The integrated circuit (IC) must be placed close to the switching MOSFET's gate terminals. Keep the
gate drive signal traces short for a clean MOSFET drive. The IC can be placed on the other side of the
PCB of switching MOSFETs.
3. Place inductor input terminal as close as possible to switching MOSFET's output terminal. Minimize the
copper area of this trace to lower electrical and magnetic field radiation, but make the trace wide
enough to carry the charging current. Do not use multiple layers in parallel for this connection.
Minimize parasitic capacitance from this area to any other trace or plane.
4. The charging current sensing resistor must be placed right next to the inductor output. Route the sense
leads connected across the sensing resistor back to the IC in the same layer, close to each other
(minimize loop area), and do not route the sense leads through a high-current path. Place decoupling
capacitor on these traces next to the IC.
5. Place output capacitor next to the sensing resistor output and ground.
6. Output capacitor ground connections need to be tied to the same copper that connects to the input
capacitor ground before connecting to system ground.
7. Use single ground connection to tie charger power ground to charger analog ground. Just beneath the
IC, use analog ground copper pour, but avoid power pins to reduce inductive and capacitive noise
coupling.
8. Route analog ground separately from power ground. Connect analog ground, and connect power
ground separately. Connect analog ground and power ground together using power pad as the single
ground connection point, or use a 0-Ω resistor to tie analog ground to power ground (power pad must
tie to analog ground in this case, if possible).
9. Decoupling capacitors must be placed next to the IC pins; make trace connection as short as possible.
10. It is critical that the exposed power pad on the backside of the IC package be soldered to the PCB
ground. Ensure that sufficient thermal vias are directly under the IC, connecting to the ground plane on
the other layers.
SLUU445B – September 2010 – Revised May 2011
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bq24707EVM for Multicell, Synchronous, Switch-Mode Charger With SMBus
Copyright © 2010–2011, Texas Instruments Incorporated
PCB Layout Guideline
9
Interface
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