Hardware Redundancy Interface; Figure 7-3 Sam Hri Interconnection - Emerson AXP1620 Installation And Use Manual

Shelf Management Alarm Module
7.5.2.1
128
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Hardware Redundancy Interface

The hardware redundancy signals of the ShMM-1500R are implemented as follows:
Cross connected ShMM-1500R present input (PRES_R#) and output (PRES_L#)
Cross connected ShMM-1500R status 0 input (SHMM_STATUS0_R) and output
(SHMM_STATUS0_L)
Cross connected redundant ShMM-1500R status 1 input (SHMM_STATUS1_R) and output
(SHMM_STATUS1_L)
Active output (ACTIVE#) that can be used on the ShMM-1500R carrier to enable interfaces
that must be exclusively driven by the active ShMM-1500R
Bi-color status LED
Note that the ACTIVE# signal is intended for use on a carrier and is not connected directly to
the peer-ShMM through the backplane. The cross-connected ShMM-1500R status signals are
asynchronous serial bit streams that are transmitted to the peer-ShMM by the FPGA and
communicate the following information: Health status, Switchover Requests, PRES_R state,
Active state, watchdog timer status, parity and other TBD data. An identical copy of the bit
stream is also sent on the redundant ShMM-1500R status signal. This information is used by
the FPGA to ensure that only one of the two connected ShMM-1500Rs goes into active mode
at a time. Figure 7-3 on page 128
As shown in the figure, the ShMM-1500R HRI incorporates a hot-swap buffer (IDT
QuickSwitch), which isolates the interface from the peer ShMM prior to FPGA configuration or
when the ShMM-1500R is powered down. The QuickSwitch device is guaranteed to be disabled
(open) when unpowered and does not have a low impedance path from any of the signal pins
to the power or ground rails. Hence, the device prevents an unpowered ShMM-1500R from
loading down the HRI of the peer ShMM-1500R. It also prevents a carrier from detecting the
ACTIVE# output as a zero; that is, active, during a ShMM-1500R power cycle or a
ShMM-1500R power supply failure.
The FPGA device contains a built-in CRC error checker for detecting soft errors in the
configuration data. When a CRC error is detected the signal LATCH_CRC_ERROR is set active
by the ShMM-1500R CRC error detection circuit, which immediately sets the
ShMM_STATUS[0:1]_L and ACTIVE# signals high. The peer ShMM-1500R, if it is not already
active upon detecting the loss of the status serial bit streams, becomes the active
ShMM-1500R.
Figure 7-3 SAM HRI Interconnection
ShMM-1500R A
ShMM-1500R A buffer
shows the HRI of the ShMM-1500R.
F_ShMM_STATUS 0
F_ShMM_STATUS 1
PRES#
GND
AXP1620 Installation and Use (6806800E23E)
Redundancy Control
ShMM-1500R B
GND
ShMM-1500R B buffer