Dram Configurations - Nvidia nForce 550 MCP User Manual

Please refer to section 3-6-1
System BIOS Cacheable
Selecting Enabled allows caching of the system BIOS ROM at F0000h-FFFFFh, resulting in
better system performance. However, if any program writes to this memory area, a system
error may result. The settings are: Enabled and Disabled.
3-6-1 DRAM Configuration
DRAM Bank Interleaving
Memclock tri-stating
Memory Hole Remapping
(CASL0CAS # latency
DRAM command Rate
Auto optimization Bottom IO
Bottom of [31:24] IO Space
DDRII Timing Item
TwTr Command Delay
Trfc0 for DIMM0
Trfc1 for DIMM1
Trfc2 for DIMM2
Trfc3 for DIMM3
<Twr> Write Recovery Time
<Trtp> precharge Time
<Trc> Row Cycle Time
<Trcd> RAS to CAS R/W Delay
<Trrd> RAS to RAS Delay
<Trp> Row precharge time
<Tras> Minimum RAS Active time 18 bus clocks
↑↓→← Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5:Previous Values
SDRAM RAS-to-CAS Delay
This field let's you insert a timing delay between the CAS and RAS strobe signals, used when
DRAM is written to, read from, or refreshed. Fast gives faster performance; and Slow gives
more stable performance. This field applies only when synchronous DRAM is installed in
the system. The settings are: 4T and 3T.
SDRAM Precharge Time
If an insufficient number of cycles is allowed for the RAS to accumulate its charge before
DRAM refresh, the refresh may be incomplete and the DRAM may fail to retain date. Fast
gives faster performance; and Slow gives more stable performance. This field applies only
when synchronous DRAM is installed in the system. The settings are: 2T and 3T.
DRAM CAS Latency
When synchronous DRAM is installed, the number of clock cycles of CAS latency depends
on the DRAM timing. The settings are: 2T and 2.5T.
Phoenix – AwardBIOS CMOS Setup Utility
DRAM Timing Settings
Enabled
Disabled
Enabled
Auto
2T
Enabled
192
Disabled
3 bus clocks
Reserved
Reserved
Reserved
Reserved
6 bus clocks
3 clocks
26 bus clocks
6 clocks
5 clocks
6 clocks
F6:Optimized Defaults
Menu Level >>
F7:Standard Defaults
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